温 暁青

MISC

• Power-Aware Testing for Low-Power VLSI Circuits

  X. Wen

  15th IEEE Int'l Conf. on Electron Devices and Solid-State Cirucits 585-588 2019年6月1日 査読有り招待有り責任著者
• The impact of production defects on the soft-error tolerance of hardened latches

  Holst S., Ma R., Wen X.

  Proceedings of the European Test Workshop 2018-May 1-6 2018年6月29日 査読有り
• Bit-Flip Errors Detection using Random Partial Don't-Care Keys for a Soft-Error-Tolerant TCAM

  I. Syafalni, T. Sasao, X. Wen

  Proceedings of the 27th International Workshop on Logic and Synthesis 124-131 2018年6月23日 査読有り
• A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application

  A. Yan, K. Yang, Z. Huang, J. Zhang, X. Fang, X. Wen

  IEEE Transactions on Circuits and Systems II: Express Briefs 66(2) 287-291 2018年6月19日 査読有り
• A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application

  A. Yan, K. Yang, Z. Huang, J. Zhang, X. Fang, X. Wen

  IEEE Transactions on Circuits and Systems II: Express Briefs 66(2) 287-291 2018年6月19日 査読有り
• A Method to Detect Bit Flips in a Soft-Error Resilient TCAM

  Infall Syafalni, Tsutomu Sasao, Xiaoqing Wen

  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37(6) 1185-1196 2018年6月1日
• The Impact of Production Defects on the Soft-Error Tolerance of Hardened Latches

  S. Holst, R. Ma, X. Wen

  Proceedings of IEEE European Test Symposium 2018年5月28日 査読有り
• Design Automation for Legacy Circuits

  I. Syafalni, K. Wakasugi, T. Yang, T. Sasao, X. Wen

  Proceedings of the 21st Workshop on Synthesis and System Integration of Mixed Information Technologies 174-179 2018年3月26日 査読有り
• Scan chain grouping for mitigating ir-drop-induced test data corruption

  Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Jun Qian

  Proceedings of the Asian Test Symposium 140-145 2018年1月24日
• Bit-Flip Errors Detection using Random Partial Don't-Care Keys for a Soft-Error-Tolerant TCAM

  I. Syafalni, T. Sasao, X. Wen

  Proceedings of the 27th International Workshop on Logic and Synthesis 124-131 2018年
• The Impact of Production Defects on the Soft-Error Tolerance of Hardened Latches

  S. Holst, R. Ma, X. Wen

  Proceedings of IEEE European Test Symposium 2018年
• Design Automation for Legacy Circuits

  I. Syafalni, K. Wakasugi, T. Yang, T. Sasao, X. Wen

  Proceedings of the 21st Workshop on Synthesis and System Integration of Mixed Information Technologies 174-179 2018年
• Analysis and mitigation or IR-Drop induced scan shift-errors

  Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen

  Proceedings - International Test Conference 2017- 1-8 2017年12月29日
• Locating Hot Spot with Justification Techniques in a Layout Design

  K. Miyase, Y. Kawano, X. Wen, S. Kajihara

  Proceedings of IEEE Workshop on RTL and High Level Testing 2017年11月30日 査読有り
• Vernier ring based pre-bond through silicon vias test in 3D ICs

  Tianming Ni, Mu Nie, Huaguo Liang, Jingchang Bian, Xiumin Xu, Xiangsheng Fang, Zhengfeng Huang, Xiaoqing Wen

  IEICE ELECTRONICS EXPRESS 14(18) 2017年9月
• Power-aware testing for low-power VLSI circuits

  Xiaoqing Wen

  2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings 585-588 2017年7月31日
• GPU-Accelerated Simulation of Small Delay Faults

  Eric Schneider, Michael A. Kochte, Stefan Holst, Xiaoqing Wen, Hans-Joachim Wunderlich

  IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 36(5) 829-841 2017年5月
• On Optimal Power-Aware Path Sensitization

  M. Sauer, J. Jiang, S. Reimer, K. Miyase, X. Wen, B. Becker, I. Polian

  Workshop of Test and Reliability for Circuits and Systems 2017年3月5日 査読有り
• Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding

  Dong Xiang, Xiaoqing Wen, Laung-Terng Wang

  IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 25(3) 942-953 2017年3月
• Locating Hot Spot with Justification Techniques in a Layout Design

  K. Miyase, Y. Kawano, X. Wen, S. Kajihara

  Proceedings of IEEE Workshop on RTL and High Level Testing 2017年