Xiaoqing Wen

Misc.

• Power-Aware Testing for Low-Power VLSI Circuits

  X. Wen

  15th IEEE Int'l Conf. on Electron Devices and Solid-State Cirucits, 585-588, Jun 1, 2019 Peer-reviewedInvitedCorresponding author
• The impact of production defects on the soft-error tolerance of hardened latches

  Holst S., Ma R., Wen X.

  Proceedings of the European Test Workshop, 2018-May 1-6, Jun 29, 2018 Peer-reviewed
• Bit-Flip Errors Detection using Random Partial Don't-Care Keys for a Soft-Error-Tolerant TCAM

  I. Syafalni, T. Sasao, X. Wen

  Proceedings of the 27th International Workshop on Logic and Synthesis, 124-131, Jun 23, 2018 Peer-reviewed
• A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application

  A. Yan, K. Yang, Z. Huang, J. Zhang, X. Fang, X. Wen

  IEEE Transactions on Circuits and Systems II: Express Briefs, 66(2) 287-291, Jun 19, 2018 Peer-reviewed
• A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application

  A. Yan, K. Yang, Z. Huang, J. Zhang, X. Fang, X. Wen

  IEEE Transactions on Circuits and Systems II: Express Briefs, 66(2) 287-291, Jun 19, 2018 Peer-reviewed
• A Method to Detect Bit Flips in a Soft-Error Resilient TCAM

  Infall Syafalni, Tsutomu Sasao, Xiaoqing Wen

  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(6) 1185-1196, Jun 1, 2018
• The Impact of Production Defects on the Soft-Error Tolerance of Hardened Latches

  S. Holst, R. Ma, X. Wen

  Proceedings of IEEE European Test Symposium, May 28, 2018 Peer-reviewed
• Design Automation for Legacy Circuits

  I. Syafalni, K. Wakasugi, T. Yang, T. Sasao, X. Wen

  Proceedings of the 21st Workshop on Synthesis and System Integration of Mixed Information Technologies, 174-179, Mar 26, 2018 Peer-reviewed
• Scan chain grouping for mitigating ir-drop-induced test data corruption

  Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Jun Qian

  Proceedings of the Asian Test Symposium, 140-145, Jan 24, 2018
• Bit-Flip Errors Detection using Random Partial Don't-Care Keys for a Soft-Error-Tolerant TCAM

  I. Syafalni, T. Sasao, X. Wen

  Proceedings of the 27th International Workshop on Logic and Synthesis, 124-131, 2018
• The Impact of Production Defects on the Soft-Error Tolerance of Hardened Latches

  S. Holst, R. Ma, X. Wen

  Proceedings of IEEE European Test Symposium, 2018
• Design Automation for Legacy Circuits

  I. Syafalni, K. Wakasugi, T. Yang, T. Sasao, X. Wen

  Proceedings of the 21st Workshop on Synthesis and System Integration of Mixed Information Technologies, 174-179, 2018
• Analysis and mitigation or IR-Drop induced scan shift-errors

  Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen

  Proceedings - International Test Conference, 2017- 1-8, Dec 29, 2017
• Locating Hot Spot with Justification Techniques in a Layout Design

  K. Miyase, Y. Kawano, X. Wen, S. Kajihara

  Proceedings of IEEE Workshop on RTL and High Level Testing, Nov 30, 2017 Peer-reviewed
• Vernier ring based pre-bond through silicon vias test in 3D ICs

  Tianming Ni, Mu Nie, Huaguo Liang, Jingchang Bian, Xiumin Xu, Xiangsheng Fang, Zhengfeng Huang, Xiaoqing Wen

  IEICE ELECTRONICS EXPRESS, 14(18), Sep, 2017
• Power-aware testing for low-power VLSI circuits

  Xiaoqing Wen

  2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings, 585-588, Jul 31, 2017
• GPU-Accelerated Simulation of Small Delay Faults

  Eric Schneider, Michael A. Kochte, Stefan Holst, Xiaoqing Wen, Hans-Joachim Wunderlich

  IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 36(5) 829-841, May, 2017
• On Optimal Power-Aware Path Sensitization

  Workshop of Test and Reliability for Circuits and Systems, Mar 5, 2017 Peer-reviewed
• Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding

  Dong Xiang, Xiaoqing Wen, Laung-Terng Wang

  IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 25(3) 942-953, Mar, 2017
• Locating Hot Spot with Justification Techniques in a Layout Design

  K. Miyase, Y. Kawano, X. Wen, S. Kajihara

  Proceedings of IEEE Workshop on RTL and High Level Testing, 2017