Cross Module Reference Cross Module Reference abbreviated as XMR is a very useful concept in Verilog HDL (as well as system Verilog). However it seems to be less known among many users of Verilog. XMR is a mechanism built into Verilog to globally reference (i.e., across the modules) to any nets, tasks, functions etc. Using XMR, one can refer to any object of a module in any other module, irrespective of whether they are present below or above its hierarchy. Hence, a XMR can be a: Downward reference OR Upward reference Consider the following hierarchy: Module A Net x Instance P of Module B Net x Instance M of Module D Net x Instance Q of Module C Net x Instance N of Module E Net x Instance R of Module B Net x Instance M of Module D Net x ...
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Showing posts with the label Verilog Tutorial
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>> Introduction >> The initial Construct >> The always Construct >> Procedural Assignments >> Block Statements >> Conditional (if-else) Statement >> Case Statement >> Loop Statements >> Examples Introduction Behavioral modeling is the highest level of abstraction in the Verilog HDL. The other modeling techniques are relatively detailed. They require some knowledge of how hardware, or hardware signals work. The abstraction in this modeling is as simple as writing the logic in C language. This is a very powerful abstraction technique. All that designer needs is the algorithm of the design, which is the basic information for any design. Most of the behavioral modeling is done using two important constructs: initial and always. All the other behavioral statements appear only inside these two structured procedure constructs. The initial Construct The statements which come under the initial construct constitute the initial block. The in...
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>> Introduction >> Differences >> Tasks >> Functions >> Examples Introduction Tasks and functions are introduced in the verilog, to provide the ability to execute common procedures from different places in a description. This helps the designer to break up large behavioral designs into smaller pieces. The designer has to abstract the similar pieces in the description and replace them either functions or tasks. This also improves the readability of the code, and hence easier to debug. Tasks and functions must be defined in a module and are local to the module. Tasks are used when: There are delay, timing, or event control constructs in the code. There is no input. There is zero output or more than one output argument. Functions are used when: The code executes in zero simulation time. The code provides only one output(return value) and has at least one input. There are no delay, timing, or event control constructs. Differences Functions Tasks Can enabl...
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>> Introduction >> The assign Statement >> Delays >> Examples Introduction Dataflow modeling is a higher level of abstraction. The designer no need have any knowledge of logic circuit. He should be aware of data flow of the design. The gate level modeling becomes very complex for a VLSI circuit. Hence dataflow modeling became a very important way of implementing the design. In dataflow modeling most of the design is implemented using continuous assignments, which are used to drive a value onto a net. The continuous assignments are made using the keyword assign . The assign statement The assign statement is used to make continuous assignment in the dataflow modeling. The assign statement usage is given below: assign out = in0 + in1; // in0 + in1 is evaluated and then assigned to out. Note: The LHS of assign statement must always be a scalar or vector net or a concatenation. It cannot be a register. Continuous statements are always active statements. Registers o...
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>> Introduction >> Gate Primitives >> Delays >> Examples Introduction In Verilog HDL a module can be defined using various levels of abstraction. There are four levels of abstraction in verilog. They are: Behavioral or algorithmic level: This is the highest level of abstraction. A module can be implemented in terms of the design algorithm. The designer no need to have any knowledge of hardware implementation. Data flow level: In this level the module is designed by specifying the data flow. Designer must how data flows between various registers of the design. Gate level: The module is implemented in terms of logic gates and interconnections between these gates. Designer should know the gate-level diagram of the design. Switch level: This is the lowest level of abstraction. The design is implemented using switches/transistors. Designer requires the knowledge of switch-level implementation details. Gate-level modeling is virtually the lowest-level of abstraction, ...
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The Verilog HDL is defined in terms of a discrete event execution model. A design consists of connected processes. Processes are objects that can be evaluated, that may have state, and that can respond to changes on their inputs to produce outputs. Processes include primitives, modules, initial and always procedural blocks, continuous assignments, asynchronous tasks, and procedural assignment statements. The following definitions helps in better understanding of scheduling and execution of events: Update event : Every change in value of a net or variable in the circuit being simulated, as well as the named event, is considered as an update event. Evaluation event : Processes are sensitive to update events. When an update event is executed, all the processes that are sensitive to that event are evaluated in an arbitrary order. The evaluation of a process is also an event, known as an evaluation event. Simulation time: It is used to refer to the time value maintained by the simulator to ...
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>> Logical Operators >> Relational Operators >> Equality Operators >> Arithmetic Operators >> Bitwise Operators >> Reduction Operators >> Shift Operators >> Conditional Operators >> Replication Operators >> Concatenation Operators >> Operator Precedence Logical Operators Symbol Description #Operators ! Logical negation One || Logical OR Two && Logical AND Two Relational Operators Symbol Description #Operators > Greater than Two < Less than Two >= Greater than or equal to Two <= Less than or equal to Two Equality Operators Symbol Description #Operators == Equality Two != Inequality Two === Case equality Two !== Case inequality Two Arithmetic Operators Symbol Description #Operators + Add Two - Substract Two * Multiply Two / Divide Two ** Power Two % Modulus Two Bitwise Operators Symbol Description #Operators ~ Bit...
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>> Value Set >> Nets >> Registers >> Integers >> Real Numbers >> Parameters >> Vectors >> Arrays >> Strings >> Time Data Type Value Set The Verilog HDL value set consists of four basic values: 0 - represents a logic zero, or a false condition. 1 - represents a logic one, or a true condition. x - represents an unknown logic value. z - represents a high-impedance state. The values 0 and 1 are logical complements of one another. Almost all of the data types in the Verilog HDL store all four basic values. Nets Nets are used to make connections between hardware elements. Nets simply reflect the value at one end(head) to the other end(tail). It means the value they carry is continuously driven by the output of a hardware element to which they are connected to. Nets are generally declared using the keyword wire . The default value of net (wire) is z. If a net has no driver, then its value is z . Registers Registers are data storage e...
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Modules communicate with external world using ports. They provide interface to the modules. A module definition contains list of ports. All ports in the list of ports must be declared in the module, ports can be one the following types: Input port, declared using keyword input . Output port, declared using keyword output . Bidirectional port, declared using keyword inout . All the ports declared are considered to be as wire by default. If a port is intended to be a wire, it is sufficient to declare it as output , input , or inout . If output port holds its value it should be declared as reg type. Ports of type input and inout cannot be declared as reg because reg variables hold values and input ports should not hold values but simply reflect the changes in the external signals they are connected to. Port Connection Rules Inputs: Always of type net ( wire ). Externally, they can be connected to reg or net type variable. Outputs: Can be of reg or net type. Externally, they must ...
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