VLSI Interview Questions - 4

1. Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates)usually limited to four?


To limit the height of the stack. The higher the stack the slower the gate will be. In NAND and NOR gates the number of gates present in the stack is usually same as the number of inputs plus one. So inputs are limited to four.

2. What are static and dynamic power dissipation w.r.t to CMOS gate?




3. Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) considering Channel Length Modulation.




4. Which is fastest among the following technologies: CMOS, BiCMOS, TTL, ECL?




5. What is a transmission gate, and what is its typical use in VLSI?




6. Draw the cross section of nMOS or pMOS.




7. What should be done to the size of a pMOS transistor inorder to increase its threshold voltage?




8. Explain the various MOSFET Capacitances and their significance.




9. On what factors does the resistance of metal depend on?


R = (p.l)/A
Where
R = Resistance of the metal.
p = Resistivity of the metal.
A = is the cross sectional area.
l = length of the metal.
With increase in length or decrease in cross sectional area resistance of the metal wire increases. Resistivity(p) is the material property which depends on temperature. In general, resistivity of metals increases with temperature.

10. Draw the layout a CMOS NAND gate.



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