VLSI Interview Questions - 6

1. Why is NAND gate preferred over NOR gate for fabrication?


NAND is a better gate for design than NOR because at the transistor level the mobility of electrons of NAND is normally three times that of holes compared to NOR and thus the NAND is a faster gate. The gate-leakage in NAND structures is much lower. If you consider t_phl and t_plh delays you will find that it is more symmetric in case of NAND (the delay profile), but for NOR, one delay is much higher than the other(obviously t_plh is higher since the higher resistance PMOSs are in series connection which again increases the resistance).

2. Which transistor has higher gain: BJT or MOSFET and why?


BJT has higher gain because it has higher transconductance.This is because the current in BJT is exponentially dependent on input where as in MOSFET it is square law.

3. Why PMOS and NMOS are sized equally in a transmission gates?


In transmission gate, PMOS and NMOS aid each other rather than competing with each other. So they are sized similarly.

4. What is SCR?


A silicon-controlled rectifier (or semiconductor-controlled rectifier) is a 4-layer solid state device that controls current flow.
An SCR is a type of rectifier, controlled by a logic gate signal. It is a 4-layered, 3-terminal device. A p-type layer acts as an anode and an n-type layer as a cathode; the p-type layer closer to the n-type(cathode) acts as a gate.

5. In CMOS digital design, why is the size of PMOS is generally higher than that of the NMOS?


In PMOS the carriers are holes whose mobility is less than the electrons, the carriers in NMOS. That means PMOS is slower than NMOS. In CMOS technology, NMOS helps in pulling down the output to ground and PMOS helps in pulling up the output to Vdd. If the sizes of PMOS and NMOS are the same, then PMOS takes long time to charge up the output node. If we have a larger PMOS than there will be more carriers to charge the node quickly and overcome the slow nature of PMOS. All this is done to get equal rise and fall times for the output node.

6. What is slack?


The slack is the time delay difference from the expected delay to the actual delay in a particular path. Slack can be positive or negative.

7. What is latch up?


A latchup is the inadvertent creation of a low-impedance path between the power supply rails of an electronic component, triggering a parasitic structure(The parasitic structure is usually equivalent to a thyristor or SCR), which then acts as a short circuit, disrupting proper functioning of the part. Depending on the circuits involved, the amount of current flow produced by this mechanism can be large enough to result in permanent destruction of the device due to electrical over stress - EOS.

8. Why is the size of inverters in buffer design gradually increased? Why not give the output of a circuit to one large inverter?


Because circuit can not drive the high output load straight away, so the load is gradually increased, by gradually increasing the size of inverters to get an optimized performance.

9. What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus?


The charge sharing problem occurs when the charge which is stored at the output node in the phase is shared among the output or junction capacitances of transistors which are in the evaluation phase. Charge sharing may degrade the output voltage level or even cause erroneous output value.
In the serially connected NMOS logic the input capacitance of each gate shares the charge with the load capacitance by which the logical levels drastically mismatched than that of the desired once. To eliminate this load capacitance must be very high compared to the input capacitance of the gate, which is generally 10 times.

10. What happens to delay if load capacitance is increased?


Delay increases.

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