Digital Design Interview Questions - 3

1. What are set up time and hold time constraints?


Set up time is the amount of time before the clock edge that the input signal needs to be stable to guarantee it is accepted properly on the clock edge.
Hold time is the amount of time after the clock edge that same input signal has to be held before changing it to make sure it is sensed properly at the clock edge.
Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable, which is known as as metastable state or quasi stable state. At the end of metastable state, the flip-flop settles down to either logic high or logic low. This whole process is known as metastability.

2. Give a circuit to divide frequency of clock cycle by two.




3. Design a divide-by-3 sequential circuit with 50% duty circle.




4. Explain different types of adder circuits.




5. Give two ways of converting a two input NAND gate to an inverter.




6. Draw a Transmission Gate-based D-Latch.




7. Design a FSM which detects the sequence 10101 from a serial line without overlapping.




8. Design a FSM which detects the sequence 10101 from a serial line with overlapping.




9. Give the design of 8x1 multiplexer using 2x1 multiplexers.




10. Design a counter which counts from 1 to 10 ( Resets to 1, after 10 ).



Comments

Anonymous said…
For some questions answers are not there can you please post the answers also..?
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