Microprocessor Interview Questions - 3

1. How many bits processor is 8086?


16-bit processor.

2. What are the sizes of data bus and address bus in 8086?


16-bit data bus, and 20-bit address bus.

3. What is the maximum addressable memory of 8086?


1MByte, because 20-bit address bus.

4. How are 32-bit addresses stored in 8086?


32-bit addresses are stored in "SEGMENT:OFFSET" format. SEGMENT and OFFSET are 16-bit values.
ADDRESS = (SEGMENT* 16) + OFFSET

5. What are the 16-bit registers that are available in 8086?


The following are the 16-bit registers that are available in 8086.

8 general purpose registers:
AX - Accumulator Register
Bx - Base Register
CX - Count Register
DX - Data Register
SP - Stack Pointer
BP - Base Pointer
SI - Source Index
DI - Destination Index

4 segment registers:
CS - Code Segment
DS - Data Segment
SS - Stack Segment
ES - Extra Segment

Others:
IP - Instruction Pointer
Flag register


6. What are the different types of address modes available in 8086?


Implied - the data value/data address is implicitly associated with the instruction.
Register - references the data in a register or in a register pair.
Immediate - the data is provided in the instruction.
Direct - the instruction operand specifies the memory address where data is located.
Register indirect - instruction specifies a register containing an address, where data is located. This addressing mode works with SI, DI, BX and BP registers.
Based - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP), the resulting value is a pointer to location where data resides.
Indexed - 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides.
Based Indexed - the contents of a base register (BX or BP) is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides.
Based Indexed with Offset - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP) and index register (SI or DI), the resulting value is a pointer to location where data resides.

7. How many flags are available in flag register? What are they?


9 flags are available, they are:
Overflow Flag
Direction Flag
Interrupt-enable Flag
Trace/Trap Flag
Sign Flag
Zero Flag
Auxiliary carry Flag
Parity Flag
Carry Flag

8. Explain the functioning of IP (instruction pointer).


IP always points to next instruction to be executed. Offset address is relative to CS (which points at the segment containing the current program). The next instruction address is obtained using IP.

9. What are the various types of interrupts present in 8086?


INTR - maskable hardware interrupt
NMI - non-maskable interrupt
Software interrupts

10. How many segments are present in 8086? What are they?


4 segments are available in 8086. They are:
Code segment
Data segment
Extra segment
Stack segment

Comments

(追記) (追記ここまで)

Popular posts from this blog

1. How do you convert a XOR gate into a buffer and a inverter (Use only one XOR gate for each)? Answer 2. Implement an 2-input AND gate using a 2x1 mux. Answer 3. What is a multiplexer? Answer A multiplexer is a combinational circuit which selects one of many input signals and directs to the only output. 4. What is a ring counter? Answer A ring counter is a type of counter composed of a circular shift register. The output of the last shift register is fed to the input of the first register. For example, in a 4-register counter, with initial register values of 1100, the repeating pattern is: 1100, 0110, 0011, 1001, 1100, so on. 5. Compare and Contrast Synchronous and Asynchronous reset. Answer Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant. The clock works as a filter for sma...
225 comments
Designing a FSM is the most common and challenging task for every digital logic designer. One of the key factors for optimizing a FSM design is the choice of state coding, which influences the complexity of the logic functions, the hardware costs of the circuits, timing issues, power usage, etc. There are several options like binary encoding, gray encoding, one-hot encoding, etc. The choice of the designer depends on the factors like technology, design specifications, etc. One-hot encoding In one-hot encoding only one bit of the state vector is asserted for any given state. All other state bits are zero. Thus if there are n states then n state flip-flops are required. As only one bit remains logic high and rest are logic low, it is called as One-hot encoding. Example : If there is a FSM, which has 5 states. Then 5 flip-flops are required to implement the FSM using one-hot encoding. The states will have the following values: S0 - 10000 S1 - 01000 S2 - 00100 S3 - 00010 S4 - 00001 Adv...
3 comments
Cross Module Reference   Cross Module Reference abbreviated as XMR is a very useful concept in Verilog HDL (as well as system Verilog). However it seems to be less known among many users of Verilog. XMR is a mechanism built into Verilog to globally reference (i.e., across the modules) to any nets, tasks, functions etc. Using XMR, one can refer to any object of a module in any other module, irrespective of whether they are present below or above its hierarchy. Hence, a XMR can be a:   Downward reference OR Upward reference   Consider the following hierarchy:     Module A   Net x   Instance P of Module B     Net x   Instance M of Module D   Net x   Instance Q of Module C   Net x   Instance N of Module E    Net x   Instance R of Module B   Net x   Instance M of Module D   Net x ...
10 comments