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Oct 13, 2025 / 5 min read
Semiconductor technology is driven by the demands of the most advanced applications. Today, these are AI and high performance computing (HPC). Large, complex system on chip (SoC) designs must satisfy the performance and feature requirements of these applications. Such chips put pressure on tools and methodology at every step of the development process, and even beyond to deployment in the field.
Test is no exception, and major advances have been required in the last few years to ensure that defective parts are screened out in production and failing chips are identified in the field before they cause catastrophic damage. Synopsys is the industry leader in semiconductor test, and accordingly has introduced many test innovations. This blog post considers several of these advanced technologies, particularly those related to test architecture.
Modern AI and HPC chips are hard to test because of their size and complexity and because they contain thousands of IP cores, many of them identical but used in different ways and connected differently. As devices have become more complex, access to device cores is more difficult, with many cores not directly accessible from test ports. At the floor plan level, abutted tiles may make it hard to find room for the structures needed to implement design for test (DFT) and built-in self-test (BIST) techniques.
Advanced nodes have new failure modes, so test engineers need to apply new fault models to ensure that the testing process covers these faults and detects most or all of the possible defects. This is leading to an exponential increase in test time and test data volume (TDV), driving up manufacturing costs and reducing profitability. Diagnosis time for failing tests is also an issue, but diagnosis support must be provided with minimal test data overhead required.
Many AI chips are used in safety-critical applications, where chip failure is a serious problem. A very low defective parts per million (DPPM) count is required, putting even more pressure on test time and coverage. Further, regular test in the field is mandatory to find parts that are heading toward failure due to environmental or aging effects. The testing process, and DFT hardware, now span individual dies, assembled packages (including multi-die options), system level, and in-field.
Meeting these challenges requires a complete test solution. Advanced fault models such as transition faults, path delay faults, and cell-aware faults must be supported. Automatic test pattern generation (ATPG) must be able to generate tests with sufficiently high fault coverage to meet DPPM targets. Both ATPG software and the hardware test architecture must support intelligent compression and scheduling to reduce test time and minimize TDV.
For efficient testing it is necessary to test multiple parts of the chip in parallel, while respecting power limits. Since often many cores are identical, pattern reuse and broadcast testing are essential. The architecture must enable high-speed test access, generally by reusing functional interfaces, and support test of replicated cores, or replicated dies in a multi-core design. A unified test architecture using modular and hierarchical test strategies is essential.
Test strategies must span across manufacturing with automatic test equipment (ATE), board-level system test, and in-field fault detection and recovery to ensure long-term reliability for mission-critical AI and HPC applications. Diagnostic support must efficiently find the cause of test failures without exploding test time or volume. Finally, all requirements for safety standards such as ISO 26262 for automobiles and other road vehicles must be satisfied.
Only Synopsys provides the methodology, tools, and IP to provide a complete test solution for the most advanced AI and HPC chips. The solution is based on the Unified Compression Architecture, a unified test infrastructure that reduces integration effort and improves consistency in fault coverage and diagnosis. This infrastructure spans all test phases of the silicon lifecycle: manufacturing, burn-in (BI), system-level test (SLT), and in-field/in-system test.
The Unified Compression Architecture is a scalable and flexible solution designed to accelerate test throughput, reduce TDV, and enable efficient diagnosis. The sequential (SEQ) compression/decompression infrastructure seamlessly integrates into various test environments, eliminating the need for phase-specific customization. Synopsys provides reusable IP blocks to embed compression logic in the design and reuse it across all test stages.
These IP blocks support multiple compression algorithms that can be tuned based on test phase requirements, such as high throughput for manufacturing, low power for SLT, and minimal footprint for in-field. Compression dramatically reduces TDV—by leveraging pattern redundancy and core similarity, especially in AI and HPC designs with identical cores. Decompression enables streaming of test patterns, reducing memory and bandwidth requirements.
The Synopsys approach provides diagnosis support with minimal test data overhead. Selective pattern expansion allows targeted data collection of failing patterns and blocks without applying full test sets uncompressed. Embedded diagnostic hooks capture fault signatures and scan responses. Fault isolation requires minimal additional data, enabling efficient debug in all phases. Machine learning (ML) correlates test results with defect signatures for faster and more accurate diagnosis.
Synopsys Streaming Fabric (SF), part of Synopsys TestMAX® DFT, is a foundational infrastructure designed to address the increasing complexity and scale of testing in AI and HPC SoCs. It enables efficient test data delivery, minimizes bottlenecks, and supports advanced test methodologies across all test phases.
Figure 1: High-bandwidth data streaming using Synopsys Streaming Fabric
Synopsys provides SF technology, including a programmable, high-speed dynamic bandwidth manager for testing complex SoCs using high bandwidth data streaming. The many advantages of SF include:
Figure 2: Benefits demonstrated using Synopsys SEQ and SF technologies
(* indicates that the value represents "up to" performance metric)
Test for AI and HPC SoCs has many challenges, due both to the size and complexity of the designs and to the need to span multiple phases. Synopsys Unified Compression Architecture and Streaming Fabric provide a unique and powerful solution to these challenges. Synopsys TestMAX enables a shift left strategy with a common footprint for easier integration, ensuring that chip developers can efficiently test with much lower TDV at all phases. To learn more about sequential compression/decompression and streaming fabric technologies, please visit the Synopsys TestMAX DFT webpage.