Synopsys HAPS-200 is the industry’s highest performance and most scalable pre-silicon prototyping system. Because of its high performance, HAPS® is used in pre-silicon software development, as well as at-speed interface validation in the system environment. The HAPS-200 6 FPGA platform has 2X performance, 3X higher capacity, faster compile times, and 4X debug capacity and bandwidth over the previous generation. HAPS-200 maintains compatibility with the HAPS ecosystem, enabling mixed systems with HAPS-100. It uses the latest AMD VersalTM Premium VP1902 Adaptive SoC. HAPS prototyping solutions, including HAPS ProtoCompiler prototyping software, are optimized to deliver the best performance. HAPS ProtoCompiler prototyping software builds on 20+ years of FPGA synthesis expertise built with the Synopsys Synplify® FPGA synthesis product line.
HAPS-200 is built on an EP-Ready Hardware Platform that allows to reconfiguration to support ZeBu-200 synchronous clocking with ZeBu Software. Read more in our blog.
HAPS is ideal for IP RTL regressions for single-clock IPs. It allows fast execution of hardware and software. It is suitable for CPUs, GPUs, NPUs, and AI-accelerators.
HAPS can help validate low-level software drivers before software/hardware validation. Several debug capabilities allow developers to monitor and debug the execution software during the SoC system bring-up.
HAPS prototyping systems are used when synthesizable RTL source code of the ASIC/system-on-chip design is available, allowing designers to develop software, verify SoC hardware, and enable system validation before the silicon is taped out.
HAPS prototyping systems are capable of at-speed interface prototyping, due to the asynchronous capabilities of the HAPS ProtoCompiler. The HAPS IP Prototyping Kit offers at-speed prototyping of Synopsys IP, allowing customers to run interoperability testing as well as compliance and certification.
"With the increasing market requirements for handling large AI computational data sets driving the need for enormous GPU and CPU computational power, the development time for NVIDIA’s next generation AI systems have become highly compressed to a yearly release cycle, necessitating best-in-class prototyping solutions. Synopsys HAPS-200 offers the fastest prototyping speed in the industry. The 50 MHz performance we have been able to achieve with HAPS-200 has been key to boosting productivity of our software development teams. We are looking forward to scaling our HAPS-200 deployment to take full advantage for our software development teams."
Narendra Konda
|Vice President, Hardware Engineering, NVIDIA
"The future of emulation and prototyping demands unprecedented performance, adaptability, and scalability. By integrating the AMD Versal Premium VP1902 adaptive SoC, with its industry-leading capacity*, performance, and debug capabilities, into Synopsys' EP-Ready platforms we're not only improving performance metrics, we're also transforming how engineering teams can validate and optimize their most ambitious new ASIC and SoC designs. Our longstanding partnership with Synopsys empowers design teams to tackle their most complex verification challenges, from AI/ML workloads to multi-die architectures, while dramatically accelerating time to market."
Salil Raje
|Sr Vice President and General Manager, Adaptive and Embedded Computing Group, AMD
*Based on AMD internal analysis in May 2023 with a 6-input LUT count to compare the Versal Premium VP1902 device versus competitor offerings.
"Synopsys is a key member of Arm Total Design, bringing critical tools and the advanced HAV capabilities to quickly and reliably validate solutions built on Arm Compute Subsystems (CSS). The new ZeBu-200 and HAPS-200 hardware platforms will also assist our mutual customers in integrating Arm CSS into their designs with improved turnaround times to meet the demanding requirements for complex data center infrastructure and automotive systems."
Kevork Kechichian
|Executive Vice President, Solutions Engineering, Arm
"Extending the modular HAV capabilities to the ZeBu Server 5 platform provides a scalable emulation roadmap to address the complexity challenges of validating AMD’s largest next-generation devices."
Alex Starr
|Corporate Fellow, AMD
"SiFive has a very large and configurable portfolio of RISC-V CPU and AI core IP. We extensively test our IP using software workloads on HAPS, which means we can run trillions of cycles per day. As next generation CPUs and AI cores become larger and more complex, we need to efficiently map them onto larger and more powerful FPGAs. With its EP-Ready hardware HAPS-200 offers us an FPGA platform to do full system emulation for reference platforms that scale from small microcontrollers all the way to large scale data center designs."
Albert Huntington
|Vice President, Platform Engineering, SiFive
"AMD has used ZeBu EP solutions for fast emulation with software workloads for a number of years. The EP-ready Hardware concept has allowed us to switch on demand, as a design matures, to a prototyping use case and significantly increase workload throughput. ZeBu-200 and HAPS-200 EP-Ready systems will enable further performance improvements to accelerate design verification and software validation."
Alex Starr
|Corporate Fellow, AMD