10 Tips for First-Pass Silicon Success in AI Chip Development BLOG Nov 06, 2025/5 min read BLOG 10 Tips for First-Pass Silicon Success in AI Chip Development By Rita Horner, Todd Koelling, Frank Schirrmeister Tags: Multi-Die, AI & Machine Learning, Test, Emulation, About Synopsys, Physical Implementation, Signoff, Virtual Prototyping, Engineering Central, Silicon Lifecycle Management, Design, HPC, Data Center, Silicon IP, Verification
How Multi-Die Designs Boost Automotive Chip Innovation BLOG Nov 04, 2025/3 min read BLOG How Multi-Die Designs Boost Automotive Chip Innovation By Sajani Patel, Hezi Saar Tags: Multi-Die, Silicon Lifecycle Management, Design, About Synopsys, Physical Implementation, Automotive, Silicon IP, Verification, Virtual Prototyping, 3DIC Design
AI Chips: Why Pre-Silicon Planning Is Critical BLOG Oct 14, 2025/3 min read BLOG AI Chips: Why Pre-Silicon Planning Is Critical By Scott Knowlton, Kamal Desai, Sumit Vishwakarma Tags: Multi-Die, AI & Machine Learning, Signal & Power Integrity, Simulation, Design, About Synopsys, Interface IP, Energy-Efficient SoCs, Foundation IP, Silicon IP, Verification, Virtual Prototyping
Shaping the Future of Semiconductor Design Through Collaboration: Synopsys Wins Multiple TSMC OIP Partner of the Year Awards BLOG Oct 01, 2025/3 min read BLOG Shaping the Future of Semiconductor Design Through Collaboration: Synopsys Wins Multiple TSMC OIP Partner of the Year Awards By Arun Bhattacharya Tags: Multi-Die, AI & Machine Learning, RF Design, About Synopsys, Interface IP, Silicon Lifecycle Management, Signal & Power Integrity, Design, Design Technology Co-Optimization, Photonic, Silicon IP, Analog Design, 3DIC Design
A Beginner’s Guide to Chiplets: 8 Best Practices for Multi-Die Designs BLOG Aug 26, 2025/4 min read BLOG A Beginner’s Guide to Chiplets: 8 Best Practices for Multi-Die Designs By Rob Kruger Tags: Multi-Die, AI & Machine Learning, Simulation, Design, About Synopsys, Interface IP, Foundation IP, Interface IP Subsystems, HPC, Data Center, Silicon IP, Verification
Simplifying AI Chip Development: Arm and Synopsys Execs Discuss Chiplet, Subsystem, and IP Integration BLOG Aug 07, 2025/3 min read BLOG Simplifying AI Chip Development: Arm and Synopsys Execs Discuss Chiplet, Subsystem, and IP Integration By Frank Malloy Tags: Executive Voices, Multi-Die, AI & Machine Learning, Design, About Synopsys, Physical Implementation, Silicon IP, Verification, Virtual Prototyping
UCIe 3.0 Is Here: Synopsys IP Solutions Are Ready BLOG Aug 05, 2025/3 min read BLOG UCIe 3.0 Is Here: Synopsys IP Solutions Are Ready By Sajani Patel, Varun Agrawal, Manuel Mota Tags: Multi-Die, Design, About Synopsys, Interface IP, Silicon IP
RTL Signoff vs. Functional Signoff: What’s the Difference? BLOG Jul 01, 2025/5 min read BLOG RTL Signoff vs. Functional Signoff: What’s the Difference? By Bradley Geden, Manoz Palaparthi Tags: Multi-Die, RTL Synthesis, Static & Formal Verification, AI & Machine Learning, Debug, Physical Verification, Test, Simulation, About Synopsys, Energy-Efficient SoCs, Signoff, Design, Verification, Formal Verification
High Bandwidth Memory (HBM) at the AI Crossroads: Customization or Standardization? BLOG May 28, 2025/3 min read BLOG High Bandwidth Memory (HBM) at the AI Crossroads: Customization or Standardization? By Greg Sorber Tags: Executive Voices, Multi-Die, AI & Machine Learning, Memory, Design, About Synopsys, Interface IP, Verification IP, HPC, Data Center, Silicon IP, Verification, 3DIC Design
Faster, More Collaborative SoC and Chiplet Architecture Exploration: Introducing Synopsys Platform Architect Development Kit (PADK) BLOG May 22, 2025/3 min read BLOG Faster, More Collaborative SoC and Chiplet Architecture Exploration: Introducing Synopsys Platform Architect Development Kit (PADK) By Kamal Desai Tags: Cloud, Multi-Die, Prototyping, Design, About Synopsys, Verification, Virtual Prototyping
Multi-Die Design Challenges: Industry Leaders Provide Insights and Guidance BLOG May 15, 2025/4 min read BLOG Multi-Die Design Challenges: Industry Leaders Provide Insights and Guidance By Frank Malloy Tags: Multi-Die, Design, About Synopsys, 3DIC Design
Synopsys Aims to Reduce Silicon Design Cycles by up to a Year in Collaboration with Arm BLOG Feb 06, 2025/2 min read BLOG Synopsys Aims to Reduce Silicon Design Cycles by up to a Year in Collaboration with Arm By Arun Bhattacharya Tags: Multi-Die, Design, About Synopsys, Interface IP, Foundation IP, Silicon IP
Synopsys Bold Prediction: 50% of New HPC Chip Designs Will Be Multi-Die in 2025 BLOG Jan 21, 2025/2 min read BLOG Synopsys Bold Prediction: 50% of New HPC Chip Designs Will Be Multi-Die in 2025 By Shekhar Kapoor, Michael Posner Tags: Multi-Die, Design, About Synopsys, 3DIC Design
Multi-Die Health and Reliability: Synopsys and TSMC Showcase UCIe Advances BLOG Jan 09, 2025/5 min read BLOG Multi-Die Health and Reliability: Synopsys and TSMC Showcase UCIe Advances By Faisal Goriawalla, Yervant Zorian Tags: Multi-Die, Silicon Lifecycle Management, About Synopsys, Interface IP, Silicon IP
Collaboration for Innovation: How Synopsys and TSMC are Advancing Chip Design BLOG Dec 05, 2024/2 min read BLOG Collaboration for Innovation: How Synopsys and TSMC are Advancing Chip Design By Synopsys Editorial Staff Tags: Multi-Die, Design, About Synopsys, Manufacturing, Foundation IP, HPC, Data Center, Silicon IP, 3DIC Design
Synopsys Introduces Industry’s First 40G UCIe IP Solution to Power High-Performance Multi-Die Designs BLOG Sep 09, 2024/4 min read BLOG Synopsys Introduces Industry’s First 40G UCIe IP Solution to Power High-Performance Multi-Die Designs By Manuel Mota Tags: Multi-Die, About Synopsys, Interface IP, Silicon IP
UCIe 2.0 - Setting the Tone for Chiplet Interoperability BLOG Aug 08, 2024/3 min read BLOG UCIe 2.0 - Setting the Tone for Chiplet Interoperability By Prasad Subudhi K. S, Deepak Nagaria, Narasimha Babu G V L Tags: Multi-Die, Engineering Central, Verification IP, Verification
Synopsys and Alchip Collaborate to Streamline the Path to Multi-die Success with Soft Chiplets BLOG Jun 17, 2024/4 min read BLOG Synopsys and Alchip Collaborate to Streamline the Path to Multi-die Success with Soft Chiplets By Manmeet Walia, Erez Shaizaf, Manuel Mota Tags: Multi-Die, About Synopsys
GUC Leverages 3DIC Compiler to Enable 2.5D/3D Multi-Die Package BLOG Jun 12, 2024/5 min read BLOG GUC Leverages 3DIC Compiler to Enable 2.5D/3D Multi-Die Package By Synopsys Editorial Staff, WeiHsun Liao Tags: Customer Spotlight, Multi-Die, Design, About Synopsys, 3DIC Design
Want to Mix and Match Dies in a Single Package? UCIe Can Get You There BLOG Apr 25, 2024/3 min read BLOG Want to Mix and Match Dies in a Single Package? UCIe Can Get You There By Michael Posner, Manuel Mota Tags: Multi-Die, About Synopsys, Interface IP, Silicon IP
Faster, Higher Capacity Emulation and Prototyping for AI Workloads BLOG Mar 20, 2024/4 min read BLOG Faster, Higher Capacity Emulation and Prototyping for AI Workloads By Samskrut Konduru Tags: Multi-Die, AI & Machine Learning, Prototyping, Emulation, About Synopsys, Verification
Industry Leaders Discuss "Overcoming the Challenges of Multi-die Systems Verification" BLOG Mar 15, 2024/8 min read BLOG Industry Leaders Discuss "Overcoming the Challenges of Multi-die Systems Verification" By Verification Expert Tags: Multi-Die, Engineering Central, Verification
Industry's First Verification IP for Arm AMBA CHI-G BLOG Mar 06, 2024/5 min read BLOG Industry's First Verification IP for Arm AMBA CHI-G By Sudhanshu Rao Tags: Multi-Die, Engineering Central, Verification IP, Verification
Synopsys AMBA CHI C2C System Verification Solutions BLOG Feb 22, 2024/5 min read BLOG Synopsys AMBA CHI C2C System Verification Solutions By Venkatesh Kudumula Tags: Multi-Die, Engineering Central, Verification IP, Verification
Avoiding Multi-Die System Re-spins with New Early Architecture Exploration Technology BLOG Jan 23, 2024/4 min read BLOG Avoiding Multi-Die System Re-spins with New Early Architecture Exploration Technology By Kamal Desai Tags: Multi-Die, Design, About Synopsys, Platform
Can 3DHI Meet the Demands of Aerospace and Government Applications? BLOG Jan 22, 2024/5 min read BLOG Can 3DHI Meet the Demands of Aerospace and Government Applications? By Kenneth Larsen, Ian Land, Rob Aitken Tags: Multi-Die, Aerospace & Government, Design, About Synopsys
2023 in Review: AI Takes Center Stage in the Eternal Quest for Innovation BLOG Dec 20, 2023/8 min read BLOG 2023 in Review: AI Takes Center Stage in the Eternal Quest for Innovation By Synopsys Editorial Staff Tags: Cloud, Multi-Die, AI & Machine Learning, About Synopsys
Synopsys and Intel Team Up on the First UCIe-Connected Chiplet-Based Test Chip BLOG Dec 14, 2023/4 min read BLOG Synopsys and Intel Team Up on the First UCIe-Connected Chiplet-Based Test Chip By Manuel Mota Tags: Multi-Die, About Synopsys, Interface IP, Silicon IP
What’s Next for Multi-Die Systems in 2024? BLOG Dec 13, 2023/5 min read BLOG What’s Next for Multi-Die Systems in 2024? By Shekhar Kapoor Tags: Multi-Die, About Synopsys
How Photonics Can Light the Way for Higher Performing Multi-Die Systems BLOG Nov 21, 2023/5 min read BLOG How Photonics Can Light the Way for Higher Performing Multi-Die Systems By Kenneth Larsen, Twan Korthorst Tags: Multi-Die, Design, About Synopsys, Photonic
Ensuring the Health and Reliability of Multi-Die Systems BLOG Oct 11, 2023/7 min read BLOG Ensuring the Health and Reliability of Multi-Die Systems By Randy Fish, Yervant Zorian, Manuel Mota, Guy Cortez Tags: Multi-Die, AI & Machine Learning, Design, About Synopsys, HPC, Data Center
Industry Insights: How Collaboration Will Accelerate Adoption of Multi-Die Systems BLOG Oct 04, 2023/6 min read BLOG Industry Insights: How Collaboration Will Accelerate Adoption of Multi-Die Systems By Synopsys Editorial Staff Tags: Multi-Die, About Synopsys
Samsung Foundry and Synopsys Accelerate Multi-Die System Design BLOG Sep 21, 2023/4 min read BLOG Samsung Foundry and Synopsys Accelerate Multi-Die System Design By Henry Sheng, Jennifer Pyon Tags: Multi-Die, Design, About Synopsys
Five Key Techniques to Accelerate Software Bring-Up for Multi-Die Systems BLOG Sep 12, 2023/7 min read BLOG Five Key Techniques to Accelerate Software Bring-Up for Multi-Die Systems By Filip Thoen, Leonard Drucker, Vivek Prasad Tags: Multi-Die, About Synopsys, Verification
Addressing Multi-Physics Effects for High-Performing Multi-Die Systems BLOG Aug 22, 2023/4 min read BLOG Addressing Multi-Physics Effects for High-Performing Multi-Die Systems By Shekhar Kapoor, Kenneth Larsen Tags: Multi-Die, Design, About Synopsys
Embracing Multi-Die Systems and Photonics for Aerospace and Government Applications BLOG Aug 03, 2023/8 min read BLOG Embracing Multi-Die Systems and Photonics for Aerospace and Government Applications By Jigesh Patel, Kenneth Larsen, Ian Land Tags: Multi-Die, Aerospace & Government, About Synopsys, Photonic
Key Considerations for Addressing Multi-Die System Verification Challenges BLOG Aug 01, 2023/6 min read BLOG Key Considerations for Addressing Multi-Die System Verification Challenges By Arturo Salz, Johannes Stahl Tags: Multi-Die, About Synopsys, Verification
New Distributed Simulation Technology for Faster Simulation of Multi-Die Systems BLOG Jul 24, 2023/4 min read BLOG New Distributed Simulation Technology for Faster Simulation of Multi-Die Systems By Taruna Reddy Tags: Multi-Die, About Synopsys, Verification
Developing the Blueprint for Multi-Die Systems with Virtual Prototyping Tools BLOG Jun 28, 2023/7 min read BLOG Developing the Blueprint for Multi-Die Systems with Virtual Prototyping Tools By Johannes Stahl, Tim Kogel Tags: Multi-Die, About Synopsys, Verification, Virtual Prototyping
Designing Electrostatic Discharge (ESD) Protection for Monolithic SoCs and Multi-Die Systems BLOG Jun 21, 2023/5 min read BLOG Designing Electrostatic Discharge (ESD) Protection for Monolithic SoCs and Multi-Die Systems By Dermott Lynch Tags: Multi-Die, Design, About Synopsys, Design Technology Co-Optimization
Synopsys and AMD Collaboration Achieves Significant Milestones for EDA Workloads BLOG Jun 13, 2023/4 min read BLOG Synopsys and AMD Collaboration Achieves Significant Milestones for EDA Workloads By Andy Tai, Ramesh Narayanaswamy Tags: Multi-Die, Design, About Synopsys, Physical Implementation, Signoff, HPC, Data Center, Verification
How Multi-Die Systems Transform the Semiconductor Industry BLOG May 23, 2023/6 min read BLOG How Multi-Die Systems Transform the Semiconductor Industry By Shekhar Kapoor Tags: Multi-Die, About Synopsys
Designing Thermal Management Solutions for Multi-Die Systems BLOG May 22, 2023/4 min read BLOG Designing Thermal Management Solutions for Multi-Die Systems By Synopsys Editorial Staff Tags: Multi-Die, About Synopsys
How Semiconductor Companies Use Multi-Die Systems BLOG May 18, 2023/6 min read BLOG How Semiconductor Companies Use Multi-Die Systems By Shekhar Kapoor Tags: Multi-Die, About Synopsys
Celebrating the 76th Anniversary of the Transistor BLOG Apr 26, 2023/6 min read BLOG Celebrating the 76th Anniversary of the Transistor By Victor Moroz, Rob Aitken Tags: Multi-Die, About Synopsys
Upgrading 3DIC Packaging for Faster AI Inference with PSMC BLOG Apr 25, 2023/7 min read BLOG Upgrading 3DIC Packaging for Faster AI Inference with PSMC By Kenneth Larsen Tags: Multi-Die, Design, About Synopsys
SNUG Silicon Valley 2023: Catalyzing the Future for Our Smart Everything World BLOG Apr 13, 2023/5 min read BLOG SNUG Silicon Valley 2023: Catalyzing the Future for Our Smart Everything World By Rob van Blommestein Tags: Multi-Die, AI & Machine Learning, Silicon Lifecycle Management, Test, Design, About Synopsys, Verification
UCIe Standard: Benefits & Requirements Explained BLOG Apr 11, 2023/4 min read BLOG UCIe Standard: Benefits & Requirements Explained By Manuel Mota Tags: Multi-Die, About Synopsys, Interface IP, Silicon IP
Discovering the Future of Multi-Die Systems BLOG Mar 31, 2023/4 min read BLOG Discovering the Future of Multi-Die Systems By Shekhar Kapoor Tags: Multi-Die, About Synopsys
UCIe PHY IP Tape-Out on TSMC N3E Process BLOG Mar 17, 2023/4 min read BLOG UCIe PHY IP Tape-Out on TSMC N3E Process By Manuel Mota Tags: Multi-Die, About Synopsys, Silicon IP
What are Multi-Die Systems? BLOG Feb 22, 2023/3 min read BLOG What are Multi-Die Systems? By Shekhar Kapoor Tags: Multi-Die, About Synopsys
Boosting Chip Design & Verification with AI EDA Tools BLOG Feb 07, 2023/5 min read BLOG Boosting Chip Design & Verification with AI EDA Tools By Shankar Krishnamoorthy Tags: Multi-Die, AI & Machine Learning, Design, About Synopsys, Verification
How Systems of Chips Take Us From Smart to Smarter BLOG Jan 19, 2023/4 min read BLOG How Systems of Chips Take Us From Smart to Smarter By Shankar Krishnamoorthy Tags: Multi-Die, AI & Machine Learning, About Synopsys
Why 2023 Holds Big Promise for Multi-Die Systems BLOG Jan 17, 2023/5 min read BLOG Why 2023 Holds Big Promise for Multi-Die Systems By Shekhar Kapoor, Michael Posner Tags: Multi-Die, About Synopsys
3 Key Technologies that Will Transform Electronic Design in 2023 BLOG Jan 03, 2023/6 min read BLOG 3 Key Technologies that Will Transform Electronic Design in 2023 By Sanjay Bali Tags: Cloud, Multi-Die, Silicon Lifecycle Management, Design, About Synopsys, 3DIC Design
2022's EDA & Chip Design Advancements BLOG Dec 19, 2022/10 min read BLOG 2022's EDA & Chip Design Advancements By Synopsys Editorial Staff Tags: Cloud, Multi-Die, AI & Machine Learning, Prototyping, Design, Emulation, About Synopsys, Interface IP, Automotive, HPC, Data Center, Silicon IP, Verification
How 3DICs Are Sparking a New Wave of Product Innovation BLOG Aug 22, 2022/5 min read BLOG How 3DICs Are Sparking a New Wave of Product Innovation By Shekhar Kapoor Tags: Multi-Die, About Synopsys
Multi-Chip Module Packaging Types for Multi-Die Designs BLOG Jul 26, 2022/6 min read BLOG Multi-Chip Module Packaging Types for Multi-Die Designs By Manuel Mota Tags: Multi-Die, About Synopsys, Silicon IP
Enhancing Chip Verification with AI and Machine Learning BLOG Jul 12, 2022/4 min read BLOG Enhancing Chip Verification with AI and Machine Learning By Rob van Blommestein Tags: Multi-Die, Static Verification, AI & Machine Learning, Debug, Simulation, About Synopsys, HPC, Data Center, Verification, Formal Verification
What is a SmartNIC? BLOG Jul 11, 2022/5 min read BLOG What is a SmartNIC? By Rita Horner Tags: Multi-Die, AI & Machine Learning, Design, Security IP, About Synopsys, Foundation IP, HPC, Data Center, Silicon IP, Verification, 3DIC Design
Data Center Journey: Data Volume Growth & Moore's Law BLOG Jun 16, 2022/6 min read BLOG Data Center Journey: Data Volume Growth & Moore's Law By Mike Gianfagna Tags: Multi-Die, AI & Machine Learning, About Synopsys, 5G Wireless, HPC, Data Center
How to Design SoCs for the SysMoore Era BLOG Feb 16, 2022/6 min read BLOG How to Design SoCs for the SysMoore Era By Dr. Ming Zhang Tags: Multi-Die, AI & Machine Learning, Design, About Synopsys, 3DIC Design
Hyper-Convergent Chip Designs: News & Trends BLOG Dec 15, 2021/2 min read BLOG Hyper-Convergent Chip Designs: News & Trends By Synopsys Editorial Staff Tags: Multi-Die, Design, About Synopsys, HPC, Data Center
What is Democratized Design? - Chip Design Process BLOG Nov 29, 2021/4 min read BLOG What is Democratized Design? - Chip Design Process By Synopsys Editorial Staff Tags: Multi-Die, Design, About Synopsys
High-Performance Computing Drives Demand for Chiplets BLOG Sep 14, 2021/5 min read BLOG High-Performance Computing Drives Demand for Chiplets By Kenneth Larsen Tags: Multi-Die, Design, About Synopsys, Interface IP, HPC, Data Center, Silicon IP
What is a Multi-Die Chip Design? BLOG Aug 09, 2021/5 min read BLOG What is a Multi-Die Chip Design? By Kenneth Larsen, Manuel Mota Tags: Multi-Die, Design, About Synopsys, Interface IP, Silicon IP
3DIC Design Optimization for Power, Performance & Area BLOG Jul 13, 2021/6 min read BLOG 3DIC Design Optimization for Power, Performance & Area By Kenneth Larsen Tags: Multi-Die, Design, About Synopsys
Die-to-Die Interfaces for Data Centers Bandwidth & Latency BLOG Jun 02, 2021/5 min read BLOG Die-to-Die Interfaces for Data Centers Bandwidth & Latency By Manuel Mota Tags: Multi-Die, About Synopsys, Interface IP, HPC, Data Center, Silicon IP
Library Characterization Tool for Advanced Node SoC Design BLOG Apr 20, 2021/3 min read BLOG Library Characterization Tool for Advanced Node SoC Design By Umang Doshi Tags: Multi-Die, Design, About Synopsys, Signoff
PrimeSim Continuum's Enables IC Hyperconvergence BLOG Apr 19, 2021/5 min read BLOG PrimeSim Continuum's Enables IC Hyperconvergence By Tom Hsieh Tags: Multi-Die, AI & Machine Learning, Design, About Synopsys
FPGA Prototyping Powers the SoC Design & Verification Process BLOG Apr 14, 2021/4 min read BLOG FPGA Prototyping Powers the SoC Design & Verification Process By Johannes Stahl Tags: Multi-Die, AI & Machine Learning, Prototyping, Design, About Synopsys, 5G Wireless, Verification
Integrated Chip Design Tools for IC Hyperconvergence BLOG Apr 06, 2021/4 min read BLOG Integrated Chip Design Tools for IC Hyperconvergence By Raja Tabet, Anand Thiruvengadam Tags: Multi-Die, AI & Machine Learning, Design, About Synopsys, HPC, Data Center, Silicon IP
How 3DIC Design Tools Enhance Productivity & Performance BLOG Mar 03, 2021/5 min read BLOG How 3DIC Design Tools Enhance Productivity & Performance By Shekhar Kapoor, Kenneth Larsen Tags: Multi-Die, Design, About Synopsys, 3DIC Design
Die-to-Die Connectivity for High-Performance Computing BLOG Nov 30, 2020/7 min read BLOG Die-to-Die Connectivity for High-Performance Computing By Scott Durrant Tags: Multi-Die, About Synopsys, HPC, Data Center, Silicon IP
Defining the AI Era with the IBM Research AI Hardware Center BLOG Oct 20, 2020/4 min read BLOG Defining the AI Era with the IBM Research AI Hardware Center By Arun Venkatachar Tags: Multi-Die, AI & Machine Learning, Emulation, About Synopsys, Interface IP, Virtual Prototyping, Design, Manufacturing, Design Technology Co-Optimization, Processor Solutions, Silicon IP, Verification, 3DIC Design