144768: 10/01/01: maxascent: verilog multiplexer
144769: 10/01/01: glen herrmannsfeldt: Re: verilog multiplexer
144770: 10/01/01: maxascent: Re: verilog multiplexer
144771: 10/01/01: Benjamin Krill: Re: verilog multiplexer
144773: 10/01/01: John_H: Re: verilog multiplexer
144779: 10/01/02: maxascent: Re: verilog multiplexer
144780: 10/01/02: ines_fr: MB debug module
144781: 10/01/02: ines_fr: MB debug module
144782: 10/01/02: karthikbalaguru: NOR-based Flash Memory - Design
144784: 10/01/02: John_H: Re: NOR-based Flash Memory - Design
144785: 10/01/02: karthikbalaguru: Re: NOR-based Flash Memory - Design
144787: 10/01/02: glen herrmannsfeldt: Re: NOR-based Flash Memory - Design
144786: 10/01/02: Weng Tianxiang: ASM hardware language definition file for Altera/Xilinx
144788: 10/01/02: glen herrmannsfeldt: Re: ASM hardware language definition file for Altera/Xilinx
144810: 10/01/06: grigio: Re: ASM hardware language definition file for Altera/Xilinx
144831: 10/01/07: RCIngham: Re: ASM hardware language definition file for Altera/Xilinx
144840: 10/01/07: RCIngham: Re: ASM hardware language definition file for Altera/Xilinx
144812: 10/01/06: Weng Tianxiang: Re: ASM hardware language definition file for Altera/Xilinx
144839: 10/01/07: Weng Tianxiang: Re: ASM hardware language definition file for Altera/Xilinx
144854: 10/01/07: Weng Tianxiang: Re: ASM hardware language definition file for Altera/Xilinx
144789: 10/01/02: Angus: [Digilab IIE board]Cable autodetection failed
144790: 10/01/03: John Adair: Re: Cable autodetection failed
144796: 10/01/04: Angus: Re: Cable autodetection failed
144797: 10/01/04: Angus: Re: Cable autodetection failed
144800: 10/01/05: John Adair: Re: Cable autodetection failed
144809: 10/01/05: Griffin: Why are my pins being removed? LIT:243 and MapLib:701 warnings
144851: 10/01/07: Mike Treseler: Re: Why are my pins being removed? LIT:243 and MapLib:701 warnings
144914: 10/01/14: Anssi Saari: Re: Solved! Why my pins were being optimized out. How do I get the
144870: 10/01/10: Griffin: Solved! Why my pins were being optimized out. How do I get the
144871: 10/01/10: Ed McGettigan: Re: Solved! Why my pins were being optimized out. How do I get the
144811: 10/01/06: David Fejes: university platform cable
144855: 10/01/07: mng: Re: university platform cable
145286: 10/02/04: eteam: Re: university platform cable
144859: 10/01/08: David Fejes: Re: university platform cable
144813: 10/01/06: Weng Tianxiang: A VHDL compiler error report in Xilinx ISE 10.1 and service pack 3
144815: 10/01/06: Nicholas Kinar: Databus crossing clock domains with data freeze
144816: 10/01/06: John_H: Re: Databus crossing clock domains with data freeze
144819: 10/01/06: Nicholas Kinar: Re: Databus crossing clock domains with data freeze
144825: 10/01/06: Nicholas Kinar: Re: Databus crossing clock domains with data freeze
144826: 10/01/06: Nicholas Kinar: Re: Databus crossing clock domains with data freeze
144818: 10/01/06: Jonathan Bromley: Re: Databus crossing clock domains with data freeze
144820: 10/01/06: Nicholas Kinar: Re: Databus crossing clock domains with data freeze
144821: 10/01/06: Nicholas Kinar: Re: Databus crossing clock domains with data freeze
144822: 10/01/06: Nicholas Kinar: Re: Databus crossing clock domains with data freeze
144828: 10/01/07: Jonathan Bromley: Re: Databus crossing clock domains with data freeze
144836: 10/01/07: Nicholas Kinar: Re: Databus crossing clock domains with data freeze
145375: 10/02/07: Al Momen: Re: Databus crossing clock domains with data freeze
145376: 10/02/07: Jonathan Bromley: Re: Databus crossing clock domains with data freeze
144829: 10/01/07: Jonathan Bromley: Re: Databus crossing clock domains with data freeze
144837: 10/01/07: Nicholas Kinar: Re: Databus crossing clock domains with data freeze
144823: 10/01/06: Nicholas Kinar: Re: Databus crossing clock domains with data freeze
144824: 10/01/06: Nicholas Kinar: Re: Databus crossing clock domains with data freeze
144827: 10/01/06: -jg: Serial Flash reaches 104MHz Quad IO speeds
144832: 10/01/07: airol: Add custom Ip to EDK - No result from sw registers
149197: 10/10/07: Firoz: Re: Add custom Ip to EDK - No result from sw registers
149204: 10/10/07: Kim Povlsen: Re: Add custom Ip to EDK - No result from sw registers
144834: 10/01/07: rk: Difference among Virtex Families, FPGA Books
144838: 10/01/07: Uwe Bonnes: Re: Difference among Virtex Families, FPGA Books
144845: 10/01/07: rk: Re: Difference among Virtex Families, FPGA Books
144843: 10/01/07: Nicholas Kinar: Re: Difference among Virtex Families, FPGA Books
144850: 10/01/07: Nicholas Kinar: Re: Difference among Virtex Families, FPGA Books
144852: 10/01/08: Peter Van Epp: Re: Difference among Virtex Families, FPGA Books
144853: 10/01/07: Kati: Re: Difference among Virtex Families, FPGA Books
144856: 10/01/07: Peter Alfke: Re: Difference among Virtex Families, FPGA Books
144857: 10/01/07: Peter Alfke: Re: Difference among Virtex Families, FPGA Books
144858: 10/01/07: John Adair: Re: Difference among Virtex Families, FPGA Books
144865: 10/01/08: rickman: Re: Difference among Virtex Families, FPGA Books
144841: 10/01/07: Tom Kotwal: new PC specs for Xilinx tools
144842: 10/01/07: whygee: Re: new PC specs for Xilinx tools
144860: 10/01/08: HT-Lab: Re: new PC specs for Xilinx tools
144861: 10/01/08: whygee: Re: new PC specs for Xilinx tools
144866: 10/01/08: whygee: Re: new PC specs for Xilinx tools
144867: 10/01/08: HT-Lab: Re: new PC specs for Xilinx tools
144846: 10/01/07: General Schvantzkoph: Re: new PC specs for Xilinx tools
144847: 10/01/07: Gabor: Re: new PC specs for Xilinx tools
144848: 10/01/07: emeb: Re: new PC specs for Xilinx tools
144849: 10/01/07: General Schvantzkoph: Re: new PC specs for Xilinx tools
144862: 10/01/08: Maik H.: Re: new PC specs for Xilinx tools
144863: 10/01/08: Tom Kotwal: Re: new PC specs for Xilinx tools
144864: 10/01/08: General Schvantzkoph: Re: new PC specs for Xilinx tools
144868: 10/01/08: General Schvantzkoph: Re: new PC specs for Xilinx tools
144869: 10/01/10: Prevailing over Technology: Re: new PC specs for Xilinx tools
144872: 10/01/11: salquraish: Programming Failed
144873: 10/01/11: Morppheu: E1 clock problem with Spartan3e...
144876: 10/01/11: Nico Coesel: Re: E1 clock problem with Spartan3e...
144893: 10/01/12: Nico Coesel: Re: E1 clock problem with Spartan3e...
145134: 10/01/29: RCIngham: Re: E1 clock problem with Spartan3e...
144885: 10/01/12: Morppheu: Re: E1 clock problem with Spartan3e...
144899: 10/01/13: rickman: Re: E1 clock problem with Spartan3e...
145117: 10/01/28: Morppheu: Re: E1 clock problem with Spartan3e...
145161: 10/01/29: rickman: Re: E1 clock problem with Spartan3e...
144874: 10/01/11: morppheu: E1 clock problem...
144888: 10/01/12: John_H: Re: E1 clock problem...
144875: 10/01/11: Test01: How to gracefully terminate the PCIe read request
144881: 10/01/11: Hal Murray: Re: How to gracefully terminate the PCIe read request
144897: 10/01/13: Hal Murray: Re: How to gracefully terminate the PCIe read request
144886: 10/01/12: Test01: Re: How to gracefully terminate the PCIe read request
144877: 10/01/11: Rick: Old School Hurts
144878: 10/01/11: Mike Treseler: Re: Old School Hurts
144882: 10/01/12: Peter Van Epp: Re: Old School Hurts
144879: 10/01/11: Andy: Re: Old School Hurts
144880: 10/01/11: Rick: Re: Old School Hurts
144883: 10/01/12: gentel: Timing errors in Post route simulation in modelsim
144890: 10/01/12: jt_eaton: Re: Timing errors in Post route simulation in modelsim
144896: 10/01/12: gentel: Re: Timing errors in Post route simulation in modelsim
144900: 10/01/13: jt_eaton: Re: Timing errors in Post route simulation in modelsim
144884: 10/01/12: gentel: Timing errors in Post route simulation in modelsim
144887: 10/01/12: jon: XC2V2000-5FF896C or XC2V2000-6FF896C Virtex II
144889: 10/01/12: John_H: Re: XC2V2000-5FF896C or XC2V2000-6FF896C Virtex II
144891: 10/01/12: Tim Climber: .sopc example for PCI Express Development Kit, Stratix II GX Edition
144892: 10/01/12: Philip: Xilinx ISE 10.1.03
144894: 10/01/12: austin: Re: Xilinx ISE 10.1.03
144895: 10/01/12: Andy Botterill: Re: Xilinx ISE 10.1.03
144898: 10/01/13: Serkan: black box module integration
144903: 10/01/14: Serkan: Re: black box module integration
144905: 10/01/14: Brian Drummond: Re: black box module integration
144906: 10/01/14: Nial Stewart: Re: black box module integration
144904: 10/01/14: Nial Stewart: Re: black box module integration
144908: 10/01/14: Serkan: Re: black box module integration
144909: 10/01/14: Serkan: Re: black box module integration
144901: 10/01/13: lonny: Virtex-5 with DDR3 running @ 50Mhz
144907: 10/01/14: =?ISO-8859-2?Q?Adam_G=F3rski?=: Re: Virtex-5 with DDR3 running @ 50Mhz
144911: 10/01/14: Nico Coesel: Re: Virtex-5 with DDR3 running @ 50Mhz
144920: 10/01/15: =?ISO-8859-2?Q?Adam_G=F3rski?=: Re: Virtex-5 with DDR3 running @ 50Mhz
144912: 10/01/14: Sean Durkin: Re: Virtex-5 with DDR3 running @ 50Mhz
144902: 10/01/13: Leland C. Scott: Which WebPack for old Spartan and Spartan-2?
144910: 10/01/14: austin: Re: Which WebPack for old Spartan and Spartan-2?
144913: 10/01/14: jjlindula@hotmail.com: SystemVerilog Verification Example using Quartus and ModelSim
144918: 10/01/15: Jonathan Bromley: Re: SystemVerilog Verification Example using Quartus and ModelSim
144919: 10/01/15: RCIngham: Re: SystemVerilog Verification Example using Quartus and ModelSim
144924: 10/01/15: maxascent: Re: SystemVerilog Verification Example using Quartus and ModelSim
144925: 10/01/15: Jonathan Bromley: Re: SystemVerilog Verification Example using Quartus and ModelSim
144926: 10/01/15: Mark Curry: Re: SystemVerilog Verification Example using Quartus and ModelSim
144928: 10/01/15: HT-Lab: Re: SystemVerilog Verification Example using Quartus and ModelSim
144959: 10/01/17: Petter Gustad: Re: SystemVerilog Verification Example using Quartus and ModelSim
144971: 10/01/18: Charles Gardiner: Re: SystemVerilog Verification Example using Quartus and ModelSim
144927: 10/01/15: Nial Stewart: Re: SystemVerilog Verification Example using Quartus and ModelSim
144929: 10/01/15: HT-Lab: Re: SystemVerilog Verification Example using Quartus and ModelSim
144931: 10/01/16: Anssi Saari: Re: SystemVerilog Verification Example using Quartus and ModelSim
144922: 10/01/15: jjlindula@hotmail.com: Re: SystemVerilog Verification Example using Quartus and ModelSim
144923: 10/01/15: jjlindula@hotmail.com: Re: SystemVerilog Verification Example using Quartus and ModelSim
144932: 10/01/15: jjlindula@hotmail.com: Re: SystemVerilog Verification Example using Quartus and ModelSim
145026: 10/01/20: jjlindula@hotmail.com: Re: SystemVerilog Verification Example using Quartus and ModelSim
145081: 10/01/25: fpgabuilder: Re: SystemVerilog Verification Example using Quartus and ModelSim
144915: 10/01/14: Leland C. Scott: Which WebPack for old Spartan and Spartan-2?
144921: 10/01/15: Brian Drummond: Re: Which WebPack for old Spartan and Spartan-2?
144930: 10/01/15: Gabor: Re: Which WebPack for old Spartan and Spartan-2?
144933: 10/01/15: ghelbig: Re: Which WebPack for old Spartan and Spartan-2?
144916: 10/01/14: Leland C. Scott: Which WebPack for old Spartan and Spartan-2?
144917: 10/01/15: Leland C. Scott: Which WebPack for old Spartan and Spartan-2?
144934: 10/01/16: Giorgos Tzampanakis: Altera Quartus II on Debian GNU/Linux
144935: 10/01/16: whygee: Re: Altera Quartus II on Debian GNU/Linux
144936: 10/01/16: General Schvantzkoph: Re: Altera Quartus II on Debian GNU/Linux
144941: 10/01/16: Anssi Saari: Re: Altera Quartus II on Debian GNU/Linux
144937: 10/01/16: General Schvantzkoph: Re: Altera Quartus II on Debian GNU/Linux
144939: 10/01/16: Anssi Saari: Re: Altera Quartus II on Debian GNU/Linux
144944: 10/01/16: Mike Treseler: Re: Altera Quartus II on Debian GNU/Linux
144945: 10/01/16: Michael S: Re: Altera Quartus II on Debian GNU/Linux
144961: 10/01/17: Brian Drummond: Re: Altera Quartus II on Debian GNU/Linux
144962: 10/01/18: Anssi Saari: Re: Altera Quartus II on Debian GNU/Linux
144975: 10/01/18: Petter Gustad: Re: Altera Quartus II on Debian GNU/Linux
144963: 10/01/18: Anssi Saari: Re: Altera Quartus II on Debian GNU/Linux
144972: 10/01/18: Petter Gustad: Re: Altera Quartus II on Debian GNU/Linux
144948: 10/01/17: Giorgos Tzampanakis: Re: Altera Quartus II on Debian GNU/Linux
144949: 10/01/17: Michael S: Re: Altera Quartus II on Debian GNU/Linux
144950: 10/01/17: General Schvantzkoph: Re: Altera Quartus II on Debian GNU/Linux
144951: 10/01/17: whygee: Re: Altera Quartus II on Debian GNU/Linux
144953: 10/01/17: whygee: Re: Altera Quartus II on Debian GNU/Linux
144955: 10/01/17: HT-Lab: Re: Altera Quartus II on Debian GNU/Linux
144970: 10/01/18: David Brown: Re: Altera Quartus II on Debian GNU/Linux
144979: 10/01/18: whygee: Re: Altera Quartus II on Debian GNU/Linux
144952: 10/01/17: General Schvantzkoph: Re: Altera Quartus II on Debian GNU/Linux
144954: 10/01/17: General Schvantzkoph: Re: Altera Quartus II on Debian GNU/Linux
144958: 10/01/17: Petter Gustad: Re: Altera Quartus II on Debian GNU/Linux
144965: 10/01/17: General Schvantzkoph: Re: Altera Quartus II on Debian GNU/Linux
144976: 10/01/18: General Schvantzkoph: Re: Altera Quartus II on Debian GNU/Linux
144938: 10/01/16: Leland C. Scott: Which WebPack for old Spartan and Spartan-2?
144940: 10/01/16: gopal_amlekar: CPLD programming sequence XC9500
144942: 10/01/16: Uwe Bonnes: Re: CPLD programming sequence XC9500
144946: 10/01/16: Leland C. Scott: Which WebPack for old Spartan and Spartan-2?
144968: 10/01/17: hassantalal: CDMA ON FPGA
144969: 10/01/17: abhishek kumar: DCM
144974: 10/01/18: Gabor: Re: DCM
144987: 10/01/18: Griffin: Using a timer in EDK 11.
144988: 10/01/18: mlajevar: working with ADC and DAC together
145003: 10/01/19: radarman: Re: working with ADC and DAC together
144989: 10/01/18: akshayvreddy: compiler output to fpga.
144997: 10/01/19: Brian Drummond: Re: compiler output to fpga.
145001: 10/01/19: Jonathan Bromley: Re: compiler output to fpga.
145014: 10/01/19: whygee: Re: compiler output to fpga.
145021: 10/01/20: Jonathan Bromley: Re: compiler output to fpga.
145000: 10/01/19: Gabor: Re: compiler output to fpga.
144991: 10/01/18: ghelbig: XST is driving me mad.
144992: 10/01/18: rickman: Re: XST is driving me mad.
144993: 10/01/18: jmiles@pop.net: Re: XST is driving me mad.
144994: 10/01/19: Jonathan Bromley: Re: XST is driving me mad.
144998: 10/01/19: Gabor: Re: XST is driving me mad.
144999: 10/01/19: johnp: Re: XST is driving me mad.
145008: 10/01/19: ghelbig: Re: XST is driving me mad.
144995: 10/01/19: Roger: Easy PC software tool - Bad experience
144996: 10/01/19: MK: Re: Easy PC software tool - Bad experience
145013: 10/01/19: Roger: Re: Easy PC software tool - Bad experience
145022: 10/01/20: Roger: Re: Easy PC software tool - Bad experience
145031: 10/01/21: Roger: Re: Easy PC software tool - Bad experience
145002: 10/01/19: colin: Re: Easy PC software tool - Bad experience
145012: 10/01/19: Roger: Re: Easy PC software tool - Bad experience
145020: 10/01/20: -jg: Re: Easy PC software tool - Bad experience
145028: 10/01/20: Gabor: Re: Easy PC software tool - Bad experience
145030: 10/01/20: -jg: Re: Easy PC software tool - Bad experience
145040: 10/01/21: -jg: Re: Easy PC software tool - Bad experience
157023: 14/09/02: <quarrie92@googlemail.com>: Re: Easy PC software tool - Bad experience
157024: 14/09/03: MK: Re: Easy PC software tool - Bad experience
145006: 10/01/19: moogyd: Xilinx ISE 8.2 Issue: Pin Name N1, N2...
145027: 10/01/20: Gabor: Re: Xilinx ISE 8.2 Issue: Pin Name N1, N2...
145280: 10/02/04: moogyd: Re: Xilinx ISE 8.2 Issue: Pin Name N1, N2...
145010: 10/01/19: Rishvanth: Post Route Simulation for IP CORES
145015: 10/01/19: axr0284: IEEE fixed_pkg not recognized in ISE 11.1
145016: 10/01/19: Amal: Re: IEEE fixed_pkg not recognized in ISE 11.1
145018: 10/01/20: HT-Lab: Re: IEEE fixed_pkg not recognized in ISE 11.1
145017: 10/01/19: Amal: Re: IEEE fixed_pkg not recognized in ISE 11.1
145019: 10/01/20: hassantalal: AWGN TESTING
145109: 10/01/27: Leendert: Re: AWGN TESTING
145023: 10/01/20: Alex: A construction of FPGA based design by a beginner
145025: 10/01/20: John_H: Re: A construction of FPGA based design by a beginner
145029: 10/01/20: Alex: Re: A construction of FPGA based design by a beginner
145024: 10/01/20: summer: USB transfer for DE2 board
145033: 10/01/21: gentel: user ip in edk
145036: 10/01/21: rickman: State Machine Initialization in Synplify Pro
145037: 10/01/21: rickman: Re: State Machine Initialization in Synplify Pro
145045: 10/01/22: Martin Thompson: Re: State Machine Initialization in Synplify Pro
145050: 10/01/22: Mike Treseler: Re: State Machine Initialization in Synplify Pro
145074: 10/01/25: Martin Thompson: Re: State Machine Initialization in Synplify Pro
145038: 10/01/21: rickman: Re: State Machine Initialization in Synplify Pro
145042: 10/01/21: John_H: Re: State Machine Initialization in Synplify Pro
145048: 10/01/22: John_H: Re: State Machine Initialization in Synplify Pro
145078: 10/01/25: Andy: Re: State Machine Initialization in Synplify Pro
145039: 10/01/22: Giorgos Tzampanakis: Icarus Verilog opinions
147476: 10/04/28: pini_45: Re: Icarus Verilog opinions
145041: 10/01/21: stephen.craven@gmail.com: Networking Board Recommendation
145044: 10/01/21: John Adair: Re: Networking Board Recommendation
145051: 10/01/22: Peter Van Epp: Re: Networking Board Recommendation
145058: 10/01/22: Ed McGettigan: Re: Networking Board Recommendation
145043: 10/01/21: Dennis Yurichev: FPGA farm
145057: 10/01/23: StoneThrower: Re: FPGA farm
145059: 10/01/23: Thomas Womack: Re: FPGA farm
145046: 10/01/22: realwood: offset constrain report confusion
145054: 10/01/22: Gabor: Re: offset constrain report confusion
145068: 10/01/24: realwood: Re: offset constrain report confusion
145071: 10/01/24: kadhiem_ayob: Re: offset constrain report confusion
145085: 10/01/26: realwood: Re: offset constrain report confusion
145115: 10/01/28: kadhiem_ayob: Re: offset constrain report confusion
145199: 10/02/01: realwood: Re: offset constrain report confusion
145047: 10/01/22: =?ISO-8859-1?B?RGlu52F5IEFr5/ZyZW4=?=: Spartan 3E Starter Kit - Power problem
145049: 10/01/22: John_H: Re: Spartan 3E Starter Kit - Power problem
145056: 10/01/23: glen herrmannsfeldt: Re: Spartan 3E Starter Kit - Power problem
145055: 10/01/22: =?ISO-8859-1?B?RGlu52F5IEFr5/ZyZW4=?=: Re: Spartan 3E Starter Kit - Power problem
145060: 10/01/23: =?ISO-8859-1?B?RGlu52F5IEFr5/ZyZW4=?=: Re: Spartan 3E Starter Kit - Power problem
145052: 10/01/22: Neil Steiner: ChipScope scripting for batch data collection?
145053: 10/01/22: emeb: Re: ChipScope scripting for batch data collection?
145061: 10/01/23: stephen.craven@gmail.com: Xilinx online documentation issues
145062: 10/01/23: akshayvreddy: Post route simulation warning
145064: 10/01/24: Muzaffer Kal: Re: Post route simulation warning
145063: 10/01/24: Alex: How to connect two BNC connectors to FPGA board?
145065: 10/01/24: =?ISO-8859-1?B?RGlu52F5IEFr5/ZyZW4=?=: Re: How to connect two BNC connectors to FPGA board?
145066: 10/01/24: Alex: Re: How to connect two BNC connectors to FPGA board?
145067: 10/01/24: Alex: Re: How to connect two BNC connectors to FPGA board?
145069: 10/01/24: John McCaskill: Re: How to connect two BNC connectors to FPGA board?
145070: 10/01/24: Alex: Re: How to connect two BNC connectors to FPGA board?
145072: 10/01/24: Pallavi: timing properties of fpga devices at sub-clock frequencies
145073: 10/01/24: -jg: Re: timing properties of fpga devices at sub-clock frequencies
145076: 10/01/25: Pallavi: Re: timing properties of fpga devices at sub-clock frequencies
145086: 10/01/26: Pallavi: Re: timing properties of fpga devices at sub-clock frequencies
145089: 10/01/26: Jonathan Bromley: Re: timing properties of fpga devices at sub-clock frequencies
145094: 10/01/27: Jonathan Bromley: Re: timing properties of fpga devices at sub-clock frequencies
145133: 10/01/29: Jonathan Bromley: Re: timing properties of fpga devices at sub-clock frequencies
145077: 10/01/25: John_H: Re: timing properties of fpga devices at sub-clock frequencies
145087: 10/01/26: Gabor: Re: timing properties of fpga devices at sub-clock frequencies
145088: 10/01/26: John_H: Re: timing properties of fpga devices at sub-clock frequencies
145091: 10/01/26: John McCaskill: Re: timing properties of fpga devices at sub-clock frequencies
145092: 10/01/26: Gabor: Re: timing properties of fpga devices at sub-clock frequencies
145103: 10/01/27: John_H: Re: timing properties of fpga devices at sub-clock frequencies
145123: 10/01/28: rickman: Re: timing properties of fpga devices at sub-clock frequencies
145124: 10/01/28: John_H: Re: timing properties of fpga devices at sub-clock frequencies
145075: 10/01/25: Kastil Jan: Achronix FPGA
145080: 10/01/25: whygee: Re: Achronix FPGA
145082: 10/01/25: stephen.craven@gmail.com: Re: Achronix FPGA
145083: 10/01/26: whygee: Re: Achronix FPGA
145090: 10/01/26: whygee: Re: Achronix FPGA
145096: 10/01/27: Jonathan Bromley: Re: Achronix FPGA
145100: 10/01/27: Jonathan Bromley: Re: Achronix FPGA
145102: 10/01/27: whygee: Re: Achronix FPGA
145084: 10/01/26: Gabor: Re: Achronix FPGA
145095: 10/01/27: maurizio.tranchero: Re: Achronix FPGA
145099: 10/01/27: untergangsprophet: Re: Achronix FPGA
145107: 10/01/27: WilliamGibb@gmail.com: Re: Achronix FPGA
145108: 10/01/28: Jan Coombs: Re: Achronix FPGA
145112: 10/01/28: maurizio.tranchero: Re: Achronix FPGA
145079: 10/01/25: xenix: simulation+configuration with Ethernet Lite MAC (xilinx)
145098: 10/01/27: CP: VHDL Manipulation and Generation Intrerface - vMAGIC 0.3.0 released
145110: 10/01/27: summer: data transfer between PC and DE2 board
145111: 10/01/27: summer: (correction)data transfer between PC and DE2 board
145118: 10/01/28: Weng Tianxiang: Thank you, SunMicrosystem
145120: 10/01/28: gabor: Re: Thank you, SunMicrosystem
145121: 10/01/28: Weng Tianxiang: Re: Thank you, SunMicrosystem
145122: 10/01/28: Weng Tianxiang: Re: Thank you, SunMicrosystem
145119: 10/01/28: Charles: FPGA Editor - Post Route Simulation after changes in Ncd file
145139: 10/01/29: kkoorndyk: Re: FPGA Editor - Post Route Simulation after changes in Ncd file
145909: 10/02/27: Jim Wu: Re: FPGA Editor - Post Route Simulation after changes in Ncd file
145125: 10/01/28: emeb: DPA vs FPGA Security?
145126: 10/01/28: untergangsprophet: Re: DPA vs FPGA Security?
145128: 10/01/28: jt_eaton: Re: DPA vs FPGA Security?
145129: 10/01/29: glen herrmannsfeldt: Re: DPA vs FPGA Security?
145130: 10/01/28: Antti: Re: DPA vs FPGA Security?
145132: 10/01/28: Kolja Sulimma: Re: DPA vs FPGA Security?
145137: 10/01/29: Gabor: Re: DPA vs FPGA Security?
145141: 10/01/29: Kolja Sulimma: Re: DPA vs FPGA Security?
145158: 10/01/29: emeb: Re: DPA vs FPGA Security?
145162: 10/01/29: austin: Re: DPA vs FPGA Security?
145165: 10/01/29: emeb: Re: DPA vs FPGA Security?
145186: 10/01/31: Pictographer: Re: DPA vs FPGA Security?
145187: 10/01/31: Symon: Re: DPA vs FPGA Security?
145207: 10/02/01: untergangsprophet: Re: DPA vs FPGA Security?
145127: 10/01/28: Sudhir Singh: Xilinx DCM: Is CLKIN_PERIOD really required
145131: 10/01/28: backhus: Re: Xilinx DCM: Is CLKIN_PERIOD really required
145136: 10/01/29: Gabor: Re: Xilinx DCM: Is CLKIN_PERIOD really required
145142: 10/01/29: austin: Re: Xilinx DCM: Is CLKIN_PERIOD really required
145173: 10/01/30: Sudhir Singh: Re: Xilinx DCM: Is CLKIN_PERIOD really required
145135: 10/01/29: jmunir: In system memory editor of Altera for Xilinx
145138: 10/01/29: Antti: Re: In system memory editor of Altera for Xilinx
145144: 10/01/29: Alan Fitch: Re: In system memory editor of Altera for Xilinx
145147: 10/01/29: jmunir: Re: In system memory editor of Altera for Xilinx
145209: 10/02/01: Petter Gustad: Re: In system memory editor of Altera for Xilinx
145213: 10/02/01: Alex Freed: Re: In system memory editor of Altera for Xilinx
145228: 10/02/02: Petter Gustad: Re: In system memory editor of Altera for Xilinx
145175: 10/01/30: Anssi Saari: Re: In system memory editor of Altera for Xilinx
145140: 10/01/29: austin: Re: In system memory editor of Altera for Xilinx
145143: 10/01/29: Antti: Re: In system memory editor of Altera for Xilinx
145145: 10/01/29: Antti: Re: In system memory editor of Altera for Xilinx
145146: 10/01/29: austin: Re: In system memory editor of Altera for Xilinx
145148: 10/01/29: Antti: Re: In system memory editor of Altera for Xilinx
145149: 10/01/29: Antti: Re: In system memory editor of Altera for Xilinx
145151: 10/01/29: General Schvantzkoph: Re: In system memory editor of Altera for Xilinx
145152: 10/01/29: Antti: Re: In system memory editor of Altera for Xilinx
145176: 10/01/30: Antti: Re: In system memory editor of Altera for Xilinx
145178: 10/01/30: Walter: Re: In system memory editor of Altera for Xilinx
145185: 10/01/31: Walter: Re: In system memory editor of Altera for Xilinx
145179: 10/01/30: Antti: Re: In system memory editor of Altera for Xilinx
145188: 10/01/31: rickman: Re: In system memory editor of Altera for Xilinx
145189: 10/01/31: rickman: Re: In system memory editor of Altera for Xilinx
145190: 10/02/01: Goran_Bilski: Re: In system memory editor of Altera for Xilinx
145191: 10/02/01: Antti: Re: In system memory editor of Altera for Xilinx
145192: 10/02/01: Goran_Bilski: Re: In system memory editor of Altera for Xilinx
145193: 10/02/01: Antti: Re: In system memory editor of Altera for Xilinx
145210: 10/02/01: Antti: Re: In system memory editor of Altera for Xilinx
145211: 10/02/01: General Schvantzkoph: Re: In system memory editor of Altera for Xilinx
145214: 10/02/01: Michael S: Re: In system memory editor of Altera for Xilinx
145215: 10/02/01: Michael S: Re: In system memory editor of Altera for Xilinx
145216: 10/02/01: Antti: Re: In system memory editor of Altera for Xilinx
145217: 10/02/01: Michael S: Re: In system memory editor of Altera for Xilinx
145221: 10/02/01: Antti: Re: In system memory editor of Altera for Xilinx
145222: 10/02/01: Antti: Re: In system memory editor of Altera for Xilinx
145150: 10/01/29: summer: usb transfer between PC and de2 board
145153: 10/01/29: EE EE: synthesizing a completely empty design for an FPGA to measure
145154: 10/01/29: Antti: Re: synthesizing a completely empty design for an FPGA to measure
145155: 10/01/29: Gabor: Re: synthesizing a completely empty design for an FPGA to measure
145156: 10/01/29: Ed McGettigan: Re: synthesizing a completely empty design for an FPGA to measure
145157: 10/01/29: Antti: Re: synthesizing a completely empty design for an FPGA to measure
145159: 10/01/29: rickman: Re: synthesizing a completely empty design for an FPGA to measure
145160: 10/01/29: Andy: Re: synthesizing a completely empty design for an FPGA to measure
145163: 10/01/29: Ed McGettigan: Re: synthesizing a completely empty design for an FPGA to measure
145164: 10/01/30: glen herrmannsfeldt: Re: synthesizing a completely empty design for an FPGA to measure ?quiescent current
145166: 10/01/29: -jg: Re: synthesizing a completely empty design for an FPGA to measure
145167: 10/01/29: Antti: Re: synthesizing a completely empty design for an FPGA to measure
145168: 10/01/29: Antti: Re: synthesizing a completely empty design for an FPGA to measure
145169: 10/01/30: -jg: Re: synthesizing a completely empty design for an FPGA to measure
145170: 10/01/30: Antti: Re: synthesizing a completely empty design for an FPGA to measure
145171: 10/01/30: -jg: Re: synthesizing a completely empty design for an FPGA to measure
145172: 10/01/30: Antti: Re: synthesizing a completely empty design for an FPGA to measure
145180: 10/01/30: -jg: Re: synthesizing a completely empty design for an FPGA to measure
145183: 10/01/31: Krzysztof Kepa: Re: synthesizing a completely empty design for an FPGA to measure quiescent current
145253: 10/02/03: saar drimer: Re: synthesizing a completely empty design for an FPGA to measure
145266: 10/02/04: Kolja Sulimma: Re: synthesizing a completely empty design for an FPGA to measure
145267: 10/02/04: Kolja Sulimma: Re: synthesizing a completely empty design for an FPGA to measure
145273: 10/02/04: Kolja Sulimma: Re: synthesizing a completely empty design for an FPGA to measure
145174: 10/01/30: zanaticul: vhdl divider
145177: 10/01/30: Mike Treseler: Re: vhdl divider
145182: 10/01/31: John_H: Re: vhdl divider
145230: 10/02/02: Kolja Sulimma: Re: vhdl divider
145181: 10/01/31: Giorgos Tzampanakis: Quartus Web Edition on Linux - no simulation?
145184: 10/01/31: Mike Treseler: Re: Quartus Web Edition on Linux - no simulation?

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