244: 94/10/01: Todd Parker: copy a GAL16V8B ?
247: 94/10/02: David Van den Bout: new PLDshell FTP site
250: 94/10/03: Richard Vireday: iFX8160 & PLDshell status
249: 94/10/03: <potral@e5sf.hweng.syr.ge.com>: PREP info needed
254: 94/10/03: Jeffrey M. Arnold: WWW server
255: 94/10/04: Seyang Yang,: Need email address of Xilinx office
256: 94/10/04: <weinhard@ipd.info.uni-karlsruhe.de>: VCC's EVC1 experiences
258: 94/10/05: Jeff Hutchings: Motorola MPA (FPGA's)
259: 94/10/05: Jeffrey David Cohen: CLI
261: 94/10/06: Edi Hiltebrand: Re: CLI
262: 94/10/07: Vladimir N. Zlatopolsky: Presentation CAD & FPGA ICs of Actel Corp.
264: 94/10/08: John R Fulton: Xilinx FPGA Pics: LCA, CLB etc.?
288: 94/10/13: Philip Freidin: Re: Xilinx FPGA Pics: LCA, CLB etc.?
265: 94/10/09: Robert W. Young: fpga FAQ?
266: 94/10/10: Bernd Meyer: Any documentation for Xilinx XNF file format?
267: 94/10/10: Aedan Coffey: Re: Any documentation for Xilinx XNF file format?
270: 94/10/10: Bob Elkind: Re: Any documentation for Xilinx XNF file format?
273: 94/10/10: MoellerInc: Re: Any documentation for Xilinx XNF file format?
285: 94/10/12: Larrie Carr: Re: Any documentation for Xilinx XNF file format?
274: 94/10/11: Philip Freidin: Re: Any documentation for Xilinx XNF file format?
268: 94/10/10: Steve Guccione: List of FPGA-based Computing Machines (10/94)
269: 94/10/10: Steve Guccione: List of FPGA based Computing Systems
272: 94/10/10: William J. Wolf: Re: List of FPGA based Computing Systems
275: 94/10/11: Jared Bytheway: Xilinx configuration
277: 94/10/11: Mike Stump: Re: Xilinx configuration
278: 94/10/11: David Van den Bout: Re: Xilinx configuration
286: 94/10/12: MoellerInc: Re: Xilinx configuration
294: 94/10/14: Jim LaLone: Re: Xilinx configuration
282: 94/10/12: Derek Coppen: Re: Xilinx configuration
287: 94/10/12: David Fowler: Re: Xilinx configuration
289: 94/10/13: Philip Freidin: Re: Xilinx configuration
290: 94/10/13: Richard Evans: Re: Xilinx configuration
276: 94/10/11: Michael P. Hartnett: Multipliers in FPGA's
283: 94/10/12: Satwant Singh: Re: Multipliers in FPGA's
279: 94/10/12: Sanjay Vishin: Memory bus based FPGA's
280: 94/10/12: Steve Golson: CALL FOR PAPERS -- 1995 PLD DESIGN CONFERENCE
281: 94/10/12: Chris Taylor: FLEX8000 architecture / routability with fixed pin-out
295: 94/10/14: Stephen J Smith: Re: FLEX8000 architecture / routability with fixed pin-out
284: 94/10/12: Daniele Beccari: ALTERA EPLDs
312: 94/10/18: G.LOCHON: Re: ALTERA EPLDs
291: 94/10/13: Graham Seaman: PALASM versions?
292: 94/10/13: <belanger002@wcsub.ctstateu.edu>: Re: PALASM versions?
293: 94/10/13: Mauro Cerisola: Re: PALASM versions?
299: 94/10/15: <ian@myhost.subdomain.domain>: Re: PALASM versions?
300: 94/10/15: Phil Ngai: in circuit programming, was Re: PALASM versions?
301: 94/10/17: David Van den Bout: Re: in circuit programming, was Re: PALASM versions?
306: 94/10/17: George Kiss: Re: in circuit programming
315: 94/10/18: David Van den Bout: Re: in circuit programming
310: 94/10/18: Phil Ngai: Re: in circuit programming, was Re: PALASM versions?
313: 94/10/18: David Van den Bout: Re: in circuit programming, was Re: PALASM versions?
296: 94/10/14: Steve Guccione: ANNOUNCE: WWW Page of FPGA-based Computing machines
297: 94/10/14: Jeffrey M. Arnold: FCCM'95 Call for Papers
298: 94/10/14: Shambhu J. Upadhyaya: CFP (final) -- Great Lakes Symposium on VLSI
302: 94/10/17: Scott Evans 408-436-4117: Re: Multipliers in FPGA's
303: 94/10/17: Garett B Choy: SRAM and antifuse for interconnects
304: 94/10/17: Bob Elkind: Re: SRAM and antifuse for interconnects
305: 94/10/17: MoellerInc: Re: SRAM and antifuse for interconnects
338: 94/10/24: David Qmd Grieve: Re: SRAM and antifuse for interconnects
342: 94/10/25: Garett B Choy: Re: SRAM and antifuse for interconnects
356: 94/10/27: Philip Freidin: Re: SRAM and antifuse for interconnects
357: 94/10/27: Bret Indrelee: Re: SRAM and antifuse for interconnects
369: 94/10/31: Andy Jones, x73313: Re: SRAM and antifuse for interconnects
393: 94/11/05: Charles Michael Heard heard@btr.com: Re: SRAM and antifuse for interconnects
307: 94/10/17: RLPersEng: Re: Synario
308: 94/10/17: RLPersEng: Re: FPGA RISC Processor
311: 94/10/18: Jeff Hutchings: Re: FPGA RISC Processor
314: 94/10/18: William J. Wolf: Re: FPGA RISC Processor
316: 94/10/18: Russell Petersen: Xilinx ROMS
320: 94/10/19: Bob Elkind: Re: Xilinx ROMS
323: 94/10/19: Russell Petersen: Re: Xilinx ROMS
335: 94/10/23: NAGARAJAN BALAKRISHNAN: Xilinx ROMS
317: 94/10/18: Enzo Liguori: Re: Multipliers in FPGA's
319: 94/10/19: Edi Hiltebrand: Xilinx v5.0 unified libraries are wasting CLBs
329: 94/10/21: Edi Hiltebrand: Re: Xilinx v5.0 unified libraries are wasting CLBs
318: 94/10/19: saurin shah: Photolithography at 313nm wavelength (Mid-UV).
321: 94/10/19: Luiz Andre' Barroso: USC Multiprocessor Testbed on the WWW
322: 94/10/19: Steve Casselman: Verilog for Synopsys vs Cadence
324: 94/10/19: Tomas Whitlock: XC3000 series FPGA with XAbel
328: 94/10/20: MoellerInc: Re: XC3000 series FPGA with XAbel
325: 94/10/19: James Hadley: Analog FPGAs
326: 94/10/20: William J. Wolf: Re: Analog FPGAs
327: 94/10/20: David Van den Bout: Re: Analog FPGAs
330: 94/10/21: Duy Loi Vu: iFX780's experiences
331: 94/10/21: Herman Rubin: FPGA's to use with other devices
332: 94/10/22: Christopher J Burian: I/O pin currents on Xilinx FPGAs?
339: 94/10/24: Andrew Wolfe: Re: I/O pin currents on Xilinx FPGAs?
346: 94/10/25: Christopher J Burian: Re: I/O pin currents on Xilinx FPGAs?
348: 94/10/26: Rick Spanbauer: Re: I/O pin currents on Xilinx FPGAs?
352: 94/10/27: MoellerInc: Re: I/O pin currents on Xilinx FPGAs?
333: 94/10/22: Bhanu Kapoor: Final Call for Participation -- PhysComp 94
334: 94/10/23: KevSteele: High Bus Drive (24mA) FPGAs/CPLDs?
337: 94/10/24: Philip Freidin: Re: High Bus Drive (24mA) FPGAs/CPLDs?
344: 94/10/25: Larrie Carr: Re: High Bus Drive (24mA) FPGAs/CPLDs?
360: 94/10/28: <mma@mack.rt66.com>: Re: High Bus Drive (24mA) FPGAs/CPLDs?
365: 94/10/30: Dennis Yelle: Metastable Immune? (Was: High Bus Drive (24mA) FPGAs/CPLDs?)
366: 94/10/30: Gregg Mack: Re: Metastable Immune? (Was: High Bus Drive (24mA) FPGAs/CPLDs?)
367: 94/10/31: Robert Perlman: Re: Metastable Immune? (Was: High Bus Drive (24mA) FPGAs/CPLDs?)
370: 94/10/31: Henry Spencer: Re: Metastable Immune? (Was: High Bus Drive (24mA) FPGAs/CPLDs?)
383: 94/11/03: Robert Perlman: Re: Metastable Immune? (Was: High Bus Drive (24mA) FPGAs/CPLDs?)
372: 94/10/31: SLO JAM: Re: High Bus Drive (24mA) FPGAs/CPLDs?
381: 94/11/02: KevSteele: Re: High Bus Drive (24mA) FPGAs/CPLDs?
382: 94/11/03: Andrew Phillips: Re: High Bus Drive (24mA) FPGAs/CPLDs?
336: 94/10/23: Timothy Barr: Re: I/O pin currents on Xilinx FPGAs?
341: 94/10/24: Rob Pfile: Re: I/O pin currents on Xilinx FPGAs?
354: 94/10/27: Philip Freidin: Re: I/O pin currents on Xilinx FPGAs?
340: 94/10/24: Nick Pomponio: Suggestions for low power FPGAs/CPLDs needed
355: 94/10/27: Philip Freidin: Re: Suggestions for low power FPGAs/CPLDs needed
343: 94/10/25: Pak K. Chan: Re: I/O pin currents on Xilinx FPGAs?
345: 94/10/25: Lee Fadden: Memory
361: 94/10/28: Ian Page: Re: Memory
347: 94/10/26: Ken Yiu: Xilinx and mentor
349: 94/10/26: Janet Tite: NIM: FPD '95 - Call for Papers
350: 94/10/26: Steve Casselman: Whats the point?
351: 94/10/27: Seong-Woon Kim: about ALTERA
368: 94/10/31: Paul Brown: Re: about ALTERA
376: 94/11/01: Larry Doolittle: Re: about ALTERA
378: 94/11/02: <belanger002@wcsub.ctstateu.edu>: Re: about ALTERA
387: 94/11/04: Paul Brown: Re: about ALTERA
353: 94/10/27: Phil Ngai: linear feedback shift registers
358: 94/10/28: Philip Freidin: Re: linear feedback shift registers
371: 94/11/01: Charles Michael Heard heard@btr.com: Re: linear feedback shift registers
373: 94/11/01: Tom Bruhns: Re: linear feedback shift registers
379: 94/11/02: <postmaster@lsantist.dfrf.nasa.gov>: Re: linear feedback shift registers
359: 94/10/28: Simon Hermann MacKay: Altera Flex project
380: 94/11/02: Steve Trimberger: FPGA Books (Was: Altera Flex project)
362: 94/10/28: Lee Fadden: FPGA
363: 94/10/28: Lee Fadden: fpga
364: 94/10/29: <K.M.>: Re: fpga

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