139493: 09/04/01: Sharan: 8b10b encoding + line encoding
139564: 09/04/03: Weng Tianxiang: Re: 8b10b encoding + line encoding
139494: 09/04/01: Antti: Altera flash FPGA with ColdFire hard core
139495: 09/04/01: Sharan: DCM vs PLL
139496: 09/04/01: <filter001@desinformation.de>: Re: DCM vs PLL
139525: 09/04/02: Symon: Re: DCM vs PLL
139497: 09/04/01: Symon: Re: DCM vs PLL
139499: 09/04/01: Nico Coesel: Re: DCM vs PLL
139501: 09/04/01: austin: Re: DCM vs PLL
139502: 09/04/01: <filter001@desinformation.de>: Re: DCM vs PLL
139505: 09/04/01: halong: Re: DCM vs PLL
139538: 09/04/02: Rob Gaddi: Re: DCM vs PLL
139504: 09/04/01: Colin: Virtex-5 DDRII SRAM Calibration Issues
139507: 09/04/01: News123: Switching an AC power socket from an FPGA
139511: 09/04/02: Symon: Re: Switching an AC power socket from an FPGA
139517: 09/04/02: News123: Re: Switching an AC power socket from an FPGA
139512: 09/04/01: -jg: Re: Switching an AC power socket from an FPGA
139518: 09/04/02: News123: Re: Switching an AC power socket from an FPGA
139539: 09/04/02: Rob Gaddi: Re: Switching an AC power socket from an FPGA
139549: 09/04/03: Brian Drummond: Re: Switching an AC power socket from an FPGA
139540: 09/04/02: gabor: Re: Switching an AC power socket from an FPGA
139509: 09/04/01: rickman: Lattice EPIC Logic Block Editor for Slice in CCU2 mode
139513: 09/04/01: rickman: Re: Lattice EPIC Logic Block Editor for Slice in CCU2 mode
139569: 09/04/03: Mike Treseler: Re: Lattice EPIC Logic Block Editor for Slice in CCU2 mode
139563: 09/04/03: rickman: Re: Lattice EPIC Logic Block Editor for Slice in CCU2 mode
139565: 09/04/03: gabor: Re: Lattice EPIC Logic Block Editor for Slice in CCU2 mode
139567: 09/04/03: rickman: Re: Lattice EPIC Logic Block Editor for Slice in CCU2 mode
139601: 09/04/06: rickman: Re: Lattice EPIC Logic Block Editor for Slice in CCU2 mode
139617: 09/04/07: <filter001@desinformation.de>: Re: Lattice EPIC Logic Block Editor for Slice in CCU2 mode
139627: 09/04/07: rickman: Re: Lattice EPIC Logic Block Editor for Slice in CCU2 mode
139519: 09/04/02: David Fejes: delays in XC95144XL CPLD
139520: 09/04/02: Antti.Lukats@googlemail.com: Re: delays in XC95144XL CPLD
139558: 09/04/03: Georg Acher: Re: delays in XC95144XL CPLD
139522: 09/04/02: David Fejes: Re: delays in XC95144XL CPLD
139532: 09/04/02: gabor: Re: delays in XC95144XL CPLD
139543: 09/04/02: -jg: Re: delays in XC95144XL CPLD
139557: 09/04/03: David Fejes: Re: delays in XC95144XL CPLD
139559: 09/04/03: -jg: Re: delays in XC95144XL CPLD
139560: 09/04/03: gabor: Re: delays in XC95144XL CPLD
139521: 09/04/02: knight: Maximum frequency
139531: 09/04/02: Brian Drummond: Re: Maximum frequency
139542: 09/04/02: Thomas Stanka: Re: Maximum frequency
139562: 09/04/03: Nico Coesel: Re: Maximum frequency
139572: 09/04/04: Matthew Hicks: Re: Maximum frequency
139523: 09/04/02: fpgauser: Can I capture the jtag TDO pin of a Spartan3AN
139524: 09/04/02: Antti.Lukats@googlemail.com: Re: Can I capture the jtag TDO pin of a Spartan3AN
139529: 09/04/02: jleslie48: Re: Can I capture the jtag TDO pin of a Spartan3AN
139534: 09/04/02: Antti.Lukats@googlemail.com: Re: Can I capture the jtag TDO pin of a Spartan3AN
139526: 09/04/02: Sharan: SSO
139527: 09/04/02: Andy: Re: SSO
139530: 09/04/02: gabor: Re: SSO
139533: 09/04/02: John Adair: Re: SSO
139551: 09/04/03: Brian Drummond: Re: SSO
139528: 09/04/02: jleslie48: Spectrum digital's xds510 usb jtag VS Xilinx Platform Cable USB are
139535: 09/04/02: aleksa: Timing constraints problem
139556: 09/04/02: aleksa: Re: Timing constraints problem
139629: 09/04/07: tullio grassi: Re: Timing constraints problem
139545: 09/04/02: jleslie48: clock multipliers, dividers, and more clocks...
139546: 09/04/02: <jprovidenza@yahoo.com>: Re: clock multipliers, dividers, and more clocks...
139548: 09/04/02: jleslie48: Re: clock multipliers, dividers, and more clocks...
139552: 09/04/03: Mark McDougall: Re: clock multipliers, dividers, and more clocks...
139584: 09/04/06: Mark McDougall: Re: clock multipliers, dividers, and more clocks...
139553: 09/04/02: Rob Gaddi: Re: clock multipliers, dividers, and more clocks...
139554: 09/04/02: jleslie48: Re: clock multipliers, dividers, and more clocks...
139555: 09/04/02: rickman: Re: clock multipliers, dividers, and more clocks...
139561: 09/04/03: gabor: Re: clock multipliers, dividers, and more clocks...
139578: 09/04/05: John Adair: Re: clock multipliers, dividers, and more clocks...
139580: 09/04/05: <mansoor.naseer@gmail.com>: Re: clock multipliers, dividers, and more clocks...
139625: 09/04/07: rickman: Re: clock multipliers, dividers, and more clocks...
139550: 09/04/02: emilymr: summer internship DSP + FPGA + Image processing
139566: 09/04/03: <jprovidenza@yahoo.com>: Xilinx Mig bus functional model?
139568: 09/04/03: MM: Xilinx AREA_GROUP constraint and relative placement
139570: 09/04/03: jack.harvard@googlemail.com: Xilinx Spartan3A XC3S700A die area?
139571: 09/04/03: Ehsan: Chipscope problem
139573: 09/04/04: MM: Re: Chipscope problem
139579: 09/04/05: MM: Re: Chipscope problem
139586: 09/04/05: MM: Re: Chipscope problem
139595: 09/04/06: MM: Re: Chipscope problem
139636: 09/04/07: MM: Re: Chipscope problem
139659: 09/04/08: MM: Re: Chipscope problem
139577: 09/04/04: Ehsan: Re: Chipscope problem
139585: 09/04/05: Ehsan: Re: Chipscope problem
139587: 09/04/05: Ehsan: Re: Chipscope problem
139594: 09/04/06: JuanC: Re: Chipscope problem
139612: 09/04/07: JuanC: Re: Chipscope problem
139635: 09/04/07: Ehsan: Re: Chipscope problem
139637: 09/04/07: Antti.Lukats@googlemail.com: Re: Chipscope problem
139574: 09/04/05: Xin Xiao: Modulo-10 counter
139575: 09/04/04: KJ: Re: Modulo-10 counter
139581: 09/04/05: Xin Xiao: Re: Modulo-10 counter
139582: 09/04/05: Jonathan Bromley: Re: Modulo-10 counter
139583: 09/04/05: News123: Re: Modulo-10 counter
139599: 09/04/07: Mark McDougall: Re: Modulo-10 counter
139633: 09/04/07: russ: Re: Modulo-10 counter
139596: 09/04/06: Dave Wilson: Re: Modulo-10 counter
139597: 09/04/06: Jonathan Bromley: Re: Modulo-10 counter
139598: 09/04/07: Mark McDougall: Re: Modulo-10 counter
139621: 09/04/07: Dave Wilson: Re: Modulo-10 counter
139634: 09/04/08: Mark McDougall: Re: Modulo-10 counter
139608: 09/04/07: Brian Drummond: Re: Modulo-10 counter
139609: 09/04/07: Jonathan Bromley: Re: Modulo-10 counter
139622: 09/04/07: Dave Wilson: Re: Modulo-10 counter
139600: 09/04/06: <jprovidenza@yahoo.com>: Re: Modulo-10 counter
139624: 09/04/07: Antti.Lukats@googlemail.com: Re: Modulo-10 counter
139673: 09/04/08: Manny: Re: Modulo-10 counter
139674: 09/04/08: Manny: Re: Modulo-10 counter
139576: 09/04/04: KJ: Re: Modulo-10 counter
139588: 09/04/05: <goouse@twinmail.de>: Re: Modulo-10 counter
139589: 09/04/06: Jonathan Bromley: Re: Modulo-10 counter
139606: 09/04/07: <goouse@twinmail.de>: Re: Modulo-10 counter
139610: 09/04/07: gabor: Re: Modulo-10 counter
139630: 09/04/07: Xin Xiao: Re: Modulo-10 counter
139623: 09/04/07: Rob Gaddi: Re: Modulo-10 counter
139626: 09/04/07: Dave Wilson: Re: Modulo-10 counter
139631: 09/04/07: Jon Elson: Re: Modulo-10 counter
139590: 09/04/06: <hassen.karray@gmail.com>: Don't understand the Partialmask option for partial reconfiguration
139759: 09/04/12: Dirk Koch: Re: Don't understand the Partialmask option for partial reconfiguration
139591: 09/04/06: Sharan: IO Type
139592: 09/04/06: gabor: Re: IO Type
139593: 09/04/06: John Eaton: xilinx webpack on ubuntu jaunty jackalope beta
139603: 09/04/07: <sheakeb517@gmail.com>: pll
139604: 09/04/07: Antti.Lukats@googlemail.com: Re: pll
139605: 09/04/07: Mark McDougall: Re: pll
139607: 09/04/07: Symon: Re: pll
139611: 09/04/07: axr0284: xilinx edk issues
139660: 09/04/08: maxascent: Re: xilinx edk issues
139613: 09/04/07: teixeira: Chipscope debug in EDK
139680: 09/04/08: Ehsan: Re: Chipscope debug in EDK
139614: 09/04/07: jsd: Virtex6 software
139616: 09/04/07: austin: Re: Virtex6 software
139618: 09/04/07: Antti.Lukats@googlemail.com: Re: Virtex6 software
139615: 09/04/07: gangireddy.p: Xilinx user constraints with respect to output clock from the design
139628: 09/04/07: maxascent: Re: Xilinx user constraints with respect to output clock from the design
139638: 09/04/08: gangireddy.p: Re: Xilinx user constraints with respect to output clock from the design
139657: 09/04/08: maxascent: Re: Xilinx user constraints with respect to output clock from the design
139710: 09/04/10: gangireddy.p: Re: Xilinx user constraints with respect to output clock from the design
139724: 09/04/10: gabor: Re: Xilinx user constraints with respect to output clock from the
139619: 09/04/07: Antti: ANN: Antti-Brain March issue released
139672: 09/04/08: Jon Elson: Re: ANN: Antti-Brain March issue released
139676: 09/04/08: Manny: Re: ANN: Antti-Brain March issue released
139679: 09/04/08: -jg: Re: ANN: Antti-Brain March issue released
139682: 09/04/08: Antti.Lukats@googlemail.com: Re: ANN: Antti-Brain March issue released
139620: 09/04/07: MM: V4 DSP48 Clock to out from P register to P output timing
139632: 09/04/07: MM: Re: V4 DSP48 Clock to out from P register to P output timing
139639: 09/04/08: kadhiem_ayob: Two stage synchroniser,how does it work?
139640: 09/04/08: Muzaffer Kal: Re: Two stage synchroniser,how does it work?
139641: 09/04/08: kadhiem_ayob: Re: Two stage synchroniser,how does it work?
139643: 09/04/08: kadhiem_ayob: Re: Two stage synchroniser,how does it work?
139646: 09/04/08: Dave Farrance: Re: Two stage synchroniser,how does it work?
139647: 09/04/08: kadhiem_ayob: Re: Two stage synchroniser,how does it work?
139649: 09/04/08: glen herrmannsfeldt: Re: Two stage synchroniser,how does it work?
139650: 09/04/08: Dave Farrance: Re: Two stage synchroniser,how does it work?
139651: 09/04/08: kadhiem_ayob: Re: Two stage synchroniser,how does it work?
139652: 09/04/08: Dave Farrance: Re: Two stage synchroniser,how does it work?
139658: 09/04/08: Brian Drummond: Re: Two stage synchroniser,how does it work?
139664: 09/04/08: kadhiem_ayob: Re: Two stage synchroniser,how does it work?
139667: 09/04/08: kadhiem_ayob: Re: Two stage synchroniser,how does it work?
139669: 09/04/08: Muzaffer Kal: Re: Two stage synchroniser,how does it work?
139691: 09/04/09: News123: Re: Two stage synchroniser,how does it work?
139692: 09/04/09: kadhiem_ayob: Re: Two stage synchroniser,how does it work?
139702: 09/04/09: Mike Treseler: Re: Two stage synchroniser,how does it work?
139645: 09/04/08: glen herrmannsfeldt: Re: Two stage synchroniser,how does it work?
139665: 09/04/08: Muzaffer Kal: Re: Two stage synchroniser,how does it work?
139642: 09/04/08: Kolja: Re: Two stage synchroniser,how does it work?
139644: 09/04/08: glen herrmannsfeldt: Re: Two stage synchroniser,how does it work?
139666: 09/04/08: djj08230: Re: Two stage synchroniser,how does it work?
139671: 09/04/08: rickman: Re: Two stage synchroniser,how does it work?
139678: 09/04/08: -jg: Re: Two stage synchroniser,how does it work?
139681: 09/04/08: rickman: Re: Two stage synchroniser,how does it work?
139696: 09/04/09: rickman: Re: Two stage synchroniser,how does it work?
139648: 09/04/08: NigelE: Re: Two stage synchroniser,how does it work?
139693: 09/04/09: Alan Fitch: Re: Two stage synchroniser,how does it work?
139653: 09/04/08: Cyclonefreak: Pin Assignment
139654: 09/04/08: <hassen.karray@gmail.com>: want to see and use Commands used by Xilinx ISE
139655: 09/04/08: Antti.Lukats@googlemail.com: Re: want to see and use Commands used by Xilinx ISE
139656: 09/04/08: <hassen.karray@gmail.com>: Re: want to see and use Commands used by Xilinx ISE
139661: 09/04/08: <chgentso@gmail.com>: Xilinx EDK 10.1 - SDRAM access using MPMC/VFBC by peripheral
139662: 09/04/08: <chgentso@gmail.com>: Re: Xilinx EDK 10.1 - SDRAM access using MPMC/VFBC by peripheral
139663: 09/04/08: <bluesea.xjtu@gmail.com>: @@@@@@@@About DSP48 used for 24bit * 18bit @@@@@@@@
139668: 09/04/08: rickman: Re: About DSP48 used for 24bit * 18bit
139670: 09/04/08: Muzaffer Kal: Re: About DSP48 used for 24bit * 18bit
139677: 09/04/09: Brian Drummond: Re: @@@@@@@@About DSP48 used for 24bit * 18bit @@@@@@@@
139683: 09/04/08: rickman: Re: About DSP48 used for 24bit * 18bit
139694: 09/04/09: <bluesea.xjtu@gmail.com>: Re: @@@@@@@@About DSP48 used for 24bit * 18bit @@@@@@@@
139695: 09/04/09: rickman: Re: About DSP48 used for 24bit * 18bit
139675: 09/04/08: techpaperx: How to insert Chipscope blocks directly in Xilinx Project Navigator
139699: 09/04/09: maxascent: Re: How to insert Chipscope blocks directly in Xilinx Project Navigator
139707: 09/04/09: techpaperx: Re: How to insert Chipscope blocks directly in Xilinx Project
139721: 09/04/10: JuanC: Re: How to insert Chipscope blocks directly in Xilinx Project
139684: 09/04/09: samece: reconfiguration in spartan 3
139685: 09/04/09: samece: Programming in Microblaze
139686: 09/04/08: Antti.Lukats@googlemail.com: Re: Programming in Microblaze
139687: 09/04/08: Antti: opencores again with problems?
139688: 09/04/09: Antti.Lukats@googlemail.com: Re: opencores again with problems?
139698: 09/04/09: Symon: Re: opencores again with problems?
139697: 09/04/09: rickman: Re: opencores again with problems?
139700: 09/04/09: rickman: Re: opencores again with problems?
139689: 09/04/09: murlary@gmail.com: The data cann't written into DDR2 when DMA burst > 64bytes at ML505
139690: 09/04/09: <bknpk@hotmail.com>: system C versus VHDL|verilog|specman ....
139701: 09/04/09: jleslie48: warning:impact:2217 error shows in the status register, CRC Error Bit
139739: 09/04/11: Antti.Lukats@googlemail.com: Re: warning:impact:2217 error shows in the status register, CRC Error
139754: 09/04/11: Mike Treseler: Re: warning:impact:2217 error shows in the status register, CRC Error
139743: 09/04/11: jleslie48: Re: warning:impact:2217 error shows in the status register, CRC Error
139744: 09/04/11: Antti.Lukats@googlemail.com: Re: warning:impact:2217 error shows in the status register, CRC Error
139746: 09/04/11: jleslie48: Re: warning:impact:2217 error shows in the status register, CRC Error
139874: 09/04/17: jleslie48: Re: warning:impact:2217 error shows in the status register, CRC Error
139703: 09/04/09: EDPHWSW: xilinx ram dual-edge?
139706: 09/04/09: <peter@xilinx.com>: Re: xilinx ram dual-edge?
139704: 09/04/09: fl: How to understand the Nearest Even mode of Xilinx in quantization
139705: 09/04/09: glen herrmannsfeldt: Re: How to understand the Nearest Even mode of Xilinx in quantization
139708: 09/04/09: fl: Re: How to understand the Nearest Even mode of Xilinx in quantization
139709: 09/04/10: Niv (KP): Noise in Stratix3?
139712: 09/04/10: Jonathan Bromley: Re: Noise in Stratix3?
139714: 09/04/10: Antti.Lukats@googlemail.com: Re: Noise in Stratix3?
139715: 09/04/10: <jprovidenza@yahoo.com>: Re: Noise in Stratix3?
139717: 09/04/10: Dave Wilson: Re: Noise in Stratix3?
139719: 09/04/10: Dave Wilson: Re: Noise in Stratix3?
139718: 09/04/10: Andy: Re: Noise in Stratix3?
139741: 09/04/11: Rob: Re: Noise in Stratix3?
140048: 09/04/25: Niv (KP): Re: Noise in Stratix3?
140049: 09/04/25: KJ: Re: Noise in Stratix3?
140053: 09/04/25: KJ: Re: Noise in Stratix3?
140050: 09/04/25: Dave Wilson: Re: Noise in Stratix3?
140052: 09/04/25: Niv (KP): Re: Noise in Stratix3?
139711: 09/04/10: Naveen.........: NCO'S
139713: 09/04/10: Jonathan Bromley: Re: NCO'S
139731: 09/04/11: Marty Ryba: Re: NCO'S
139732: 09/04/10: rickman: Re: NCO'S
139716: 09/04/10: Antti: S3A starterkit weird behaviou (mini quiz)
139735: 09/04/11: Arnim: Re: S3A starterkit weird behaviou (mini quiz)
139737: 09/04/11: Arnim: Re: S3A starterkit weird behaviou (mini quiz)
139738: 09/04/11: kadhiem_ayob: Re: S3A starterkit weird behaviou (mini quiz)
139823: 09/04/15: Jonathan Bromley: Re: S3A starterkit weird behaviou (mini quiz)
139826: 09/04/15: Pete Fraser: Re: S3A starterkit weird behaviou (mini quiz)
139830: 09/04/15: glen herrmannsfeldt: Re: S3A starterkit weird behaviou (mini quiz)
139736: 09/04/11: Antti.Lukats@googlemail.com: Re: S3A starterkit weird behaviou (mini quiz)
139822: 09/04/15: halong: Re: S3A starterkit weird behaviou (mini quiz)
139827: 09/04/15: Antti.Lukats@googlemail.com: Re: S3A starterkit weird behaviou (mini quiz)
139720: 09/04/10: aleksa: Strange order of BRAM data bus connections
139722: 09/04/10: Antti.Lukats@googlemail.com: Re: Strange order of BRAM data bus connections
139723: 09/04/10: aleksa: Re: Strange order of BRAM data bus connections
139725: 09/04/10: rickman: Re: Strange order of BRAM data bus connections
139726: 09/04/10: gabor: Re: Strange order of BRAM data bus connections
139727: 09/04/10: aleksa: Re: Strange order of BRAM data bus connections
139728: 09/04/10: aleksa: Re: Strange order of BRAM data bus connections
139729: 09/04/10: axr0284: Avnet spartan 3A design issue
139734: 09/04/10: Antti.Lukats@googlemail.com: Re: Avnet spartan 3A design issue
139747: 09/04/11: Muzaffer Kal: Re: Avnet spartan 3A design issue
139733: 09/04/10: rickman: Getting efficient logic synthesis
139740: 09/04/11: Andy: Re: Getting efficient logic synthesis
139757: 09/04/12: Dirk Koch: Re: Getting efficient logic synthesis
139758: 09/04/11: rickman: Re: Getting efficient logic synthesis
139760: 09/04/11: rickman: Re: Getting efficient logic synthesis
139742: 09/04/11: Ged: buy XSA-50
139755: 09/04/11: <ales.gorkic@gmail.com>: Re: buy XSA-50
139762: 09/04/12: John Adair: Re: buy XSA-50
139766: 09/04/13: <mansoor.naseer@gmail.com>: Re: buy XSA-50
139768: 09/04/13: james: Re: buy XSA-50
139748: 09/04/11: <fpgaasicdesigner@gmail.com>: Decimation clock
139749: 09/04/11: rickman: Re: Decimation clock
139752: 09/04/11: Muzaffer Kal: Re: Decimation clock
139751: 09/04/11: <fpgaasicdesigner@gmail.com>: Re: Decimation clock
139753: 09/04/11: <monurlu@gmail.com>: Microblaze GPIO API functions
139756: 09/04/11: Muzaffer Kal: Re: Microblaze GPIO API functions
139763: 09/04/12: <monurlu@gmail.com>: Re: Microblaze GPIO API functions
139761: 09/04/12: shereen.ahmed: Irregular LDPC
139764: 09/04/12: Mike Treseler: Re: Irregular LDPC
139767: 09/04/13: Pablo: XUPV2P + uClinux
139769: 09/04/13: Jonathan Bromley: Stupid question about COE files
139771: 09/04/13: Antti.Lukats@googlemail.com: Re: Stupid question about COE files
139777: 09/04/13: <ales.gorkic@gmail.com>: Re: Stupid question about COE files
139778: 09/04/13: <ales.gorkic@gmail.com>: Re: Stupid question about COE files
139785: 09/04/13: Antti.Lukats@googlemail.com: Re: Stupid question about COE files
139770: 09/04/13: JSreeniv: Processor returns-Explanation
139776: 09/04/13: News123: Re: Processor returns-Explanation
139782: 09/04/14: Brian Drummond: Re: Processor returns-Explanation
139772: 09/04/13: axr0284: microblaze and flash access
139773: 09/04/13: gabor: Re: microblaze and flash access
139775: 09/04/13: axr0284: Re: microblaze and flash access
139774: 09/04/13: ivan: Xilinx ISE bug, or?
139779: 09/04/13: Mike Harrison: Re: Xilinx ISE bug, or?
139780: 09/04/13: ivan: Re: Xilinx ISE bug, or?
139783: 09/04/13: halong: Re: Xilinx ISE bug, or?
139797: 09/04/14: axr0284: Re: Xilinx ISE bug, or?
139801: 09/04/14: gabor: Re: Xilinx ISE bug, or?
139837: 09/04/15: <wooster.berty@gmail.com>: Re: Xilinx ISE bug, or?
139847: 09/04/16: Walter Gallegos: Re: Xilinx ISE bug, or?
139856: 09/04/16: Mike Harrison: Re: Xilinx ISE bug, or?
139781: 09/04/13: Vikram: Find FPGA updates On Twitter
139784: 09/04/13: Jack Klein: Re: Find FPGA updates On Twitter
139803: 09/04/14: Symon: Re: Find FPGA updates On Twitter
139816: 09/04/14: Benjamin Couillard: Re: Find FPGA updates On Twitter
139786: 09/04/13: acd: Low-cost Altera FPGA roadmap
139787: 09/04/13: Antti.Lukats@googlemail.com: Re: Low-cost Altera FPGA roadmap
139788: 09/04/14: Petter Gustad: Re: Low-cost Altera FPGA roadmap
139792: 09/04/14: Petter Gustad: Re: Low-cost Altera FPGA roadmap
139798: 09/04/14: David Brown: Re: Low-cost Altera FPGA roadmap
139818: 09/04/15: Petter Gustad: Re: Low-cost Altera FPGA roadmap
139789: 09/04/14: Antti.Lukats@googlemail.com: Re: Low-cost Altera FPGA roadmap
139793: 09/04/14: acd: Re: Low-cost Altera FPGA roadmap
139795: 09/04/14: Antti.Lukats@googlemail.com: Re: Low-cost Altera FPGA roadmap
139802: 09/04/14: gabor: Re: Low-cost Altera FPGA roadmap
139806: 09/04/14: <MadHatter7@myself.com>: Re: Low-cost Altera FPGA roadmap
139809: 09/04/14: rickman: Re: Low-cost Altera FPGA roadmap
139810: 09/04/14: rickman: Re: Low-cost Altera FPGA roadmap
139812: 09/04/14: Antti.Lukats@googlemail.com: Re: Low-cost Altera FPGA roadmap
139814: 09/04/14: gabor: Re: Low-cost Altera FPGA roadmap
139790: 09/04/14: <ales.gorkic@gmail.com>: Mobile low power DDR SDRAM and MIG
139791: 09/04/14: Antti.Lukats@googlemail.com: Re: Mobile low power DDR SDRAM and MIG
139794: 09/04/14: <ales.gorkic@gmail.com>: Re: Mobile low power DDR SDRAM and MIG
139796: 09/04/14: Antti.Lukats@googlemail.com: Re: Mobile low power DDR SDRAM and MIG
139799: 09/04/14: gabor: Re: Mobile low power DDR SDRAM and MIG
139813: 09/04/14: Nico Coesel: Re: Mobile low power DDR SDRAM and MIG
139811: 09/04/14: <ales.gorkic@gmail.com>: Re: Mobile low power DDR SDRAM and MIG
139820: 09/04/15: Bryan: Re: Mobile low power DDR SDRAM and MIG
139800: 09/04/14: axr0284: microblaze and data bus matching access to external memory
139804: 09/04/14: Sharan: reset & analog circuits
139805: 09/04/14: Dave Farrance: Re: reset & analog circuits
139815: 09/04/14: KJ: Re: reset & analog circuits
139807: 09/04/14: Sharanbr: Re: reset & analog circuits
139846: 09/04/16: RCIngham: Re: reset & analog circuits
139808: 09/04/14: renupriya: Ethernet on Altera FPGA: Help required
139817: 09/04/15: Mark McDougall: Re: Ethernet on Altera FPGA: Help required
139819: 09/04/15: Ben_Quem: What is the minimum acceptable slack on a signal
139821: 09/04/15: <filter001@desinformation.de>: Re: What is the minimum acceptable slack on a signal
139824: 09/04/15: austin: Re: What is the minimum acceptable slack on a signal
139825: 09/04/15: KJ: Re: What is the minimum acceptable slack on a signal
139831: 09/04/15: glen herrmannsfeldt: Re: What is the minimum acceptable slack on a signal
139843: 09/04/16: Ben_Quem: Re: What is the minimum acceptable slack on a signal
139855: 09/04/16: Kolja: Re: What is the minimum acceptable slack on a signal
139828: 09/04/15: =?ISO-8859-1?Q?Nicolas_Herv=E9?=: installation of ISE & EDK 10.1.03 on OpenSuse 10.3
139851: 09/04/16: =?ISO-8859-1?Q?Nicolas_Herv=E9?=: Re: installation of ISE & EDK 10.1.03 on OpenSuse 10.3
139829: 09/04/15: JSreeniv: sync timer register
139834: 09/04/15: gabor: Re: sync timer register
139832: 09/04/15: jean-francois hasson: Synchronous clocking between Cyclone III and SDRAM
139833: 09/04/15: Mike Treseler: Re: Synchronous clocking between Cyclone III and SDRAM
139835: 09/04/15: kadhiem_ayob: Re: Synchronous clocking between Cyclone III and SDRAM
139836: 09/04/15: kadhiem_ayob: Re: Synchronous clocking between Cyclone III and SDRAM
139838: 09/04/16: Mark McDougall: Re: Synchronous clocking between Cyclone III and SDRAM
139839: 09/04/15: rickman: Re: Synchronous clocking between Cyclone III and SDRAM
139841: 09/04/16: kadhiem_ayob: Re: Synchronous clocking between Cyclone III and SDRAM
139852: 09/04/16: Nico Coesel: Re: Synchronous clocking between Cyclone III and SDRAM
139866: 09/04/17: Nico Coesel: Re: Synchronous clocking between Cyclone III and SDRAM
139902: 09/04/18: Nico Coesel: Re: Synchronous clocking between Cyclone III and SDRAM
139840: 09/04/15: <jeanfrancois62@gmail.com>: Re: Synchronous clocking between Cyclone III and SDRAM
139853: 09/04/16: rickman: Re: Synchronous clocking between Cyclone III and SDRAM
139842: 09/04/16: oliver.hofherr@googlemail.com: How to constraint the In&Outputs of an ADC in XILINX ISE 9.2 (Virtex
139854: 09/04/16: axr0284: Re: How to constraint the In&Outputs of an ADC in XILINX ISE 9.2
139858: 09/04/16: mng: Re: How to constraint the In&Outputs of an ADC in XILINX ISE 9.2
139860: 09/04/17: olliH: Re: How to constraint the In&Outputs of an ADC in XILINX ISE 9.2
139877: 09/04/17: mng: Re: How to constraint the In&Outputs of an ADC in XILINX ISE 9.2
140064: 09/04/27: olliH: Re: How to constraint the In&Outputs of an ADC in XILINX ISE 9.2
139844: 09/04/16: Ben_Quem: OFFSET OUT
139845: 09/04/16: Ben_Quem: OFFSET OUT
139848: 09/04/16: gabor: Re: OFFSET OUT
139849: 09/04/16: gert1999: Xilinx Impact cable not found
139861: 09/04/17: Dave Pollum: Re: Xilinx Impact cable not found
139863: 09/04/17: <geert.debaere28@gmail.com>: Re: Xilinx Impact cable not found
139850: 09/04/16: axr0284: microblaze and interrupt question
139857: 09/04/16: axr0284: xilinx SDK issues
139859: 09/04/17: Markus Fras: EDIF generation with Synopsys Design Compiler version B-2008.09
139862: 09/04/17: Partha: Mapping FIFO into BRAM
140357: 09/05/10: anand: Re: Mapping FIFO into BRAM
139865: 09/04/17: jleslie48: fpga locks up with slow signal, spartan chip, pin type issues.
139875: 09/04/17: jleslie48: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139886: 09/04/18: Brian Drummond: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139900: 09/04/18: Brian Drummond: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139914: 09/04/19: Brian Drummond: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139961: 09/04/21: Brian Drummond: Re: FPGA lockup with pinout report view. was: fpga locks up with slow signal, spartan chip, pin type issues.
139962: 09/04/20: jleslie48: Re: FPGA lockup with pinout report view. was: fpga locks up with slow
139891: 09/04/18: jleslie48: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139903: 09/04/18: jleslie48: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139905: 09/04/18: jleslie48: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139915: 09/04/19: jleslie48: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139945: 09/04/20: jleslie48: FPGA lockup with pinout report view. was: fpga locks up with slow
139946: 09/04/20: jleslie48: Re: FPGA lockup with pinout report view. was: fpga locks up with slow
139947: 09/04/20: glen herrmannsfeldt: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139949: 09/04/20: jleslie48: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139951: 09/04/20: djj08230: Re: FPGA lockup with pinout report view. was: fpga locks up with slow
139954: 09/04/20: rickman: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139955: 09/04/20: jleslie48: Re: FPGA lockup with pinout report view. was: fpga locks up with slow
139957: 09/04/20: jleslie48: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139963: 09/04/21: djj08230: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139964: 09/04/21: Antti.Lukats@googlemail.com: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139970: 09/04/21: jleslie48: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139971: 09/04/21: Antti.Lukats@googlemail.com: Re: fpga locks up with slow signal, spartan chip, pin type issues.
140020: 09/04/24: Brian Drummond: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139972: 09/04/21: jleslie48: partial workaround found! was:Re: fpga locks up with slow signal,
139975: 09/04/21: jleslie48: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139976: 09/04/21: jleslie48: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139979: 09/04/21: Brian Davis: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139996: 09/04/22: jleslie48: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139998: 09/04/23: Antti.Lukats@googlemail.com: Re: fpga locks up with slow signal, spartan chip, pin type issues.
140002: 09/04/23: jleslie48: Re: fpga locks up with slow signal, spartan chip, pin type issues.
140003: 09/04/23: Antti.Lukats@googlemail.com: Re: fpga locks up with slow signal, spartan chip, pin type issues.
140004: 09/04/23: Antti.Lukats@googlemail.com: Re: fpga locks up with slow signal, spartan chip, pin type issues.
140010: 09/04/23: jleslie48: Re: fpga locks up with slow signal, spartan chip, pin type issues.
140011: 09/04/23: rickman: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139867: 09/04/17: Antti: Virtex-6 shipping?
139868: 09/04/17: Antti.Lukats@googlemail.com: Re: Virtex-6 shipping?
139870: 09/04/17: Tommy Thorn: Re: Virtex-6 shipping?
141445: 09/06/24: Ed McGettigan: Re: Virtex-6 shipping?
141459: 09/06/24: Uwe Bonnes: Re: Virtex-6 shipping?
141469: 09/06/25: Uwe Bonnes: Re: Virtex-6 shipping?
141506: 09/06/26: Brian Drummond: Re: Virtex-6 shipping?
141447: 09/06/24: Antti.Lukats@googlemail.com: Re: Virtex-6 shipping?
141463: 09/06/24: Antti.Lukats@googlemail.com: Re: Virtex-6 shipping?
141468: 09/06/25: Poojan Wagh: Re: Virtex-6 shipping?
141507: 09/06/25: Antti.Lukats@googlemail.com: Re: Virtex-6 shipping?
141512: 09/06/26: Dirk Koch: Re: Virtex-6 shipping?
141582: 09/06/28: Gerhard Hoffmann: Re: Virtex-6 shipping?
139869: 09/04/17: jleslie48: even with re-run all old elements are still in there using ISE 10.1?
139871: 09/04/17: jleslie48: Re: even with re-run all old elements are still in there using ISE
139872: 09/04/17: Ged: FPGA Buying
139873: 09/04/17: Antti.Lukats@googlemail.com: Re: FPGA Buying
139887: 09/04/18: John Adair: Re: FPGA Buying
139876: 09/04/18: whygee: Dual-frequency quartz oscillator with a FPGA ?
139878: 09/04/17: Antti.Lukats@googlemail.com: Re: Dual-frequency quartz oscillator with a FPGA ?
139879: 09/04/17: Peter Alfke: Re: Dual-frequency quartz oscillator with a FPGA ?
139880: 09/04/17: Antti.Lukats@googlemail.com: Re: Dual-frequency quartz oscillator with a FPGA ?
139881: 09/04/17: Antti.Lukats@googlemail.com: Re: Dual-frequency quartz oscillator with a FPGA ?
139882: 09/04/18: whygee: Re: Dual-frequency quartz oscillator with a FPGA ?
139883: 09/04/18: -jg: Re: Dual-frequency quartz oscillator with a FPGA ?
139885: 09/04/18: whygee: Re: Dual-frequency quartz oscillator with a FPGA ?
139889: 09/04/18: whygee: Re: Dual-frequency quartz oscillator with a FPGA ?
139890: 09/04/18: David Spencer: Re: Dual-frequency quartz oscillator with a FPGA ?
139892: 09/04/18: whygee: Re: Dual-frequency quartz oscillator with a FPGA ?
139901: 09/04/18: Brian Drummond: Re: Dual-frequency quartz oscillator with a FPGA ?
139907: 09/04/19: whygee: Re: Dual-frequency quartz oscillator with a FPGA ?
139913: 09/04/19: Brian Drummond: Re: Dual-frequency quartz oscillator with a FPGA ?
139920: 09/04/19: whygee: PLL ratios (was Re: Dual-frequency quartz oscillator with a FPGA
139928: 09/04/20: Brian Drummond: Re: PLL ratios (was Re: Dual-frequency quartz oscillator with a FPGA ?)
139931: 09/04/20: whygee: Re: PLL ratios (was Re: Dual-frequency quartz oscillator with a FPGA
139934: 09/04/20: glen herrmannsfeldt: Re: PLL ratios (was Re: Dual-frequency quartz oscillator with a FPGA ?)
139938: 09/04/20: Brian Drummond: Re: PLL ratios (was Re: Dual-frequency quartz oscillator with a FPGA ?)
139941: 09/04/20: glen herrmannsfeldt: Re: PLL ratios (was Re: Dual-frequency quartz oscillator with a FPGA ?)
139937: 09/04/20: Brian Drummond: Re: PLL ratios (was Re: Dual-frequency quartz oscillator with a FPGA ?)
139932: 09/04/20: whygee: Re: PLL ratios (was Re: Dual-frequency quartz oscillator with a FPGA
139958: 09/04/20: Gavin Scott: Re: Dual-frequency quartz oscillator with a FPGA ?
139960: 09/04/21: whygee: Re: Dual-frequency quartz oscillator with a FPGA ?
139908: 09/04/19: whygee: Re: Dual-frequency quartz oscillator with a FPGA ?
139918: 09/04/19: whygee: Re: Dual-frequency quartz oscillator with a FPGA ?
139953: 09/04/20: whygee: Re: FPGA Internal reset
139884: 09/04/18: Andrew Holme: Re: Dual-frequency quartz oscillator with a FPGA ?
139888: 09/04/18: John Adair: Re: Dual-frequency quartz oscillator with a FPGA ?
139898: 09/04/18: gabor: Re: Dual-frequency quartz oscillator with a FPGA ?
139904: 09/04/18: -jg: Re: Dual-frequency quartz oscillator with a FPGA ?
139911: 09/04/18: -jg: Re: Dual-frequency quartz oscillator with a FPGA ?
139933: 09/04/19: Antti.Lukats@googlemail.com: Re: PLL ratios (was Re: Dual-frequency quartz oscillator with a FPGA
139942: 09/04/20: gabor: re: FPGA Inernal reset
139893: 09/04/18: mooo: Why is XST optimizing away my registers and how do I stop it?
139894: 09/04/18: Antti.Lukats@googlemail.com: Re: Why is XST optimizing away my registers and how do I stop it?
139896: 09/04/18: glen herrmannsfeldt: Re: Why is XST optimizing away my registers and how do I stop it?
139930: 09/04/20: Ben Jackson: Re: Why is XST optimizing away my registers and how do I stop it?
139895: 09/04/18: mooo: Re: Why is XST optimizing away my registers and how do I stop it?
139899: 09/04/18: gabor: Re: Why is XST optimizing away my registers and how do I stop it?
139943: 09/04/20: gabor: Re: Why is XST optimizing away my registers and how do I stop it?
139952: 09/04/20: rickman: Re: Why is XST optimizing away my registers and how do I stop it?
139969: 09/04/21: Poojan Wagh: Re: Why is XST optimizing away my registers and how do I stop it?
139974: 09/04/21: Muzaffer Kal: Re: Why is XST optimizing away my registers and how do I stop it?
139897: 09/04/18: Alex Freed: source for Spartan 3E chips
139906: 09/04/18: Chris Abele: Re: source for Spartan 3E chips
139980: 09/04/21: <rayzengyan@gmail.com>: Re: source for Spartan 3E chips
139982: 09/04/22: Alex Freed: Re: source for Spartan 3E chips
139986: 09/04/22: gabor: Re: source for Spartan 3E chips
139909: 09/04/18: Darcio Prestes: Atari VCS 2600 FPGA Cartridge
139912: 09/04/19: Gregory Estrade: Re: Atari VCS 2600 FPGA Cartridge
139919: 09/04/19: whygee: Re: Atari VCS 2600 FPGA Cartridge
139922: 09/04/19: whygee: Re: Atari VCS 2600 FPGA Cartridge
139924: 09/04/19: whygee: Re: Atari VCS 2600 FPGA Cartridge
139916: 09/04/19: Darcio Prestes: Re: Atari VCS 2600 FPGA Cartridge
139917: 09/04/19: Antti.Lukats@googlemail.com: Re: Atari VCS 2600 FPGA Cartridge
139921: 09/04/19: Darcio Prestes: Re: Atari VCS 2600 FPGA Cartridge
139923: 09/04/19: Darcio Prestes: Re: Atari VCS 2600 FPGA Cartridge
139925: 09/04/19: Darcio Prestes: Re: Atari VCS 2600 FPGA Cartridge
139926: 09/04/19: Frank Buss: Re: Atari VCS 2600 FPGA Cartridge
139927: 09/04/19: Nico Coesel: Re: Atari VCS 2600 FPGA Cartridge
139939: 09/04/20: Frank Buss: Re: Atari VCS 2600 FPGA Cartridge
139940: 09/04/20: Mike Harrison: Re: Atari VCS 2600 FPGA Cartridge
139977: 09/04/21: Mike Harrison: Re: Atari VCS 2600 FPGA Cartridge
139935: 09/04/20: Gregory Estrade: Re: Atari VCS 2600 FPGA Cartridge
139973: 09/04/21: Darcio Prestes: Re: Atari VCS 2600 FPGA Cartridge
139929: 09/04/19: <'use_real_email'>: Help me I am a new techie on FPGA
139959: 09/04/21: News123: Re: Help me I am a new techie on FPGA
139936: 09/04/20: Bert_Paris: Igloo nano Starter Kit
139944: 09/04/20: Benjamin Couillard: ISE 10.1 installation troubles on windows Vista 32bit
139948: 09/04/20: glen herrmannsfeldt: Re: ISE 10.1 installation troubles on windows Vista 32bit
139950: 09/04/20: Benjamin Couillard: Re: ISE 10.1 installation troubles on windows Vista 32bit
139978: 09/04/21: LittleAlex: Re: ISE 10.1 installation troubles on windows Vista 32bit
139981: 09/04/22: Bert_Paris: Re: ISE 10.1 installation troubles on windows Vista 32bit
139995: 09/04/23: Brian Drummond: Re: ISE 10.1 installation troubles on windows Vista 32bit
140141: 09/04/30: MikeWhy: Re: ISE 10.1 installation troubles on windows Vista 32bit
140339: 09/05/09: MikeWhy: Re: ISE 10.1 installation troubles on windows Vista 32bit
140336: 09/05/09: andip1982: Re: ISE 10.1 installation troubles on windows Vista 32bit
139965: 09/04/21: HT-Lab: new FPGA vendor
139966: 09/04/21: whygee: Re: new FPGA vendor
139967: 09/04/21: Antti.Lukats@googlemail.com: Re: new FPGA vendor
139968: 09/04/21: HT-Lab: Re: new FPGA vendor
139983: 09/04/22: luudee: ISE 11.1 still no MP support :(
139987: 09/04/22: General Schvantzkoph: Re: ISE 11.1 still no MP support :(
139988: 09/04/22: rickman: Re: ISE 11.1 still no MP support :(
139989: 09/04/22: General Schvantzkoph: Re: ISE 11.1 still no MP support :(
139984: 09/04/22: <'use_real_email'>: problem with high speed data transfer
139985: 09/04/22: gabor: Re: problem with high speed data transfer
140000: 09/04/23: <'use_real_email'>: Re: problem with high speed data transfer
140242: 09/05/05: mingyuexin: Re: problem with high speed data transfer
140008: 09/04/23: Andy: Re: problem with high speed data transfer
139990: 09/04/22: MM: Differences in PAR results when running standalone vs. from ISE
139991: 09/04/22: <jprovidenza@yahoo.com>: MIG DDR2 controller functional model available
139992: 09/04/22: Mike Treseler: Re: MIG DDR2 controller functional model available
139994: 09/04/22: Mike Treseler: Re: MIG DDR2 controller functional model available
139993: 09/04/22: <jprovidenza@yahoo.com>: Re: MIG DDR2 controller functional model available
140016: 09/04/23: gabor: Re: MIG DDR2 controller functional model available
140017: 09/04/23: <jprovidenza@yahoo.com>: Re: MIG DDR2 controller functional model available
139997: 09/04/23: Antti: TODAY, April 27th, says Xilinx
139999: 09/04/23: Antti.Lukats@googlemail.com: Re: TODAY, April 27th, says Xilinx
140001: 09/04/23: Frank van Eijkelenburg: Variable phase shift in a DCM_SP -> MAX_STEPS
140005: 09/04/23: <'use_real_email'>: (Actel)Want Clock on Global Network , but input is normal I/O
140006: 09/04/23: Antti.Lukats@googlemail.com: Re: (Actel)Want Clock on Global Network , but input is normal I/O
140014: 09/04/23: <'use_real_email'>: Re: (Actel)Want Clock on Global Network , but input is normal I/O
140015: 09/04/23: Antti.Lukats@googlemail.com: Re: (Actel)Want Clock on Global Network , but input is normal I/O
140007: 09/04/23: <barme2i@gmail.com>: How to put area routing constraints in a xilinx flow
140009: 09/04/23: Antti.Lukats@googlemail.com: Re: How to put area routing constraints in a xilinx flow
140036: 09/04/24: MM: Re: How to put area routing constraints in a xilinx flow
140080: 09/04/27: MM: Re: How to put area routing constraints in a xilinx flow
140012: 09/04/23: <barme2i@gmail.com>: Re: How to put area routing constraints in a xilinx flow
140013: 09/04/23: Antti.Lukats@googlemail.com: Re: How to put area routing constraints in a xilinx flow
140065: 09/04/27: <barme2i@gmail.com>: Re: How to put area routing constraints in a xilinx flow
140018: 09/04/23: Andy Botterill: how to create multiple gatelevel files from multiple rtl files during
140019: 09/04/23: <gil@radix20.com>: FPGA board with ARM9
140025: 09/04/24: =?ISO-8859-1?Q?St=E9phane_Goujet?=: Re: FPGA board with ARM9
140026: 09/04/24: Lars: Re: FPGA board with ARM9
140037: 09/04/24: <gil@radix20.com>: Re: FPGA board with ARM9
140041: 09/04/25: =?ISO-8859-1?Q?St=E9phane_Goujet?=: Re: FPGA board with ARM9
140081: 09/04/27: =?ISO-8859-1?Q?St=E9phane_Goujet?=: Re: FPGA board with ARM9
140038: 09/04/24: <gil@radix20.com>: Re: FPGA board with ARM9
140075: 09/04/27: <gil@radix20.com>: Re: FPGA board with ARM9
140076: 09/04/27: <gil@radix20.com>: Re: FPGA board with ARM9
140021: 09/04/23: Baron Samedi: Seeking open-source operating system abstraction
140022: 09/04/24: whygee: Re: some soft-processors
140525: 09/05/15: MikeWhy: Re: some soft-processors
140564: 09/05/18: MikeWhy: Re: some soft-processors
140023: 09/04/24: Antti: some soft-processors
140024: 09/04/24: Antti.Lukats@googlemail.com: Re: some soft-processors
140255: 09/05/06: <jetmarc@hotmail.com>: Re: some soft-processors
140260: 09/05/06: Antti.Lukats@googlemail.com: Re: some soft-processors
140511: 09/05/15: Tommy Thorn: Re: some soft-processors
140533: 09/05/15: Antti.Lukats@googlemail.com: Re: some soft-processors
140549: 09/05/16: -jg: Re: some soft-processors
140556: 09/05/17: Antti.Lukats@googlemail.com: Re: some soft-processors
140561: 09/05/17: -jg: Re: some soft-processors
140632: 09/05/20: -jg: Re: some soft-processors
140644: 09/05/20: Antti.Lukats@googlemail.com: Re: some soft-processors
140027: 09/04/24: Ruzica: Modelsim GTP_DUAL not recognized
140028: 09/04/24: Jonathan Bromley: Re: Modelsim GTP_DUAL not recognized
140031: 09/04/24: Jonathan Bromley: Re: Modelsim GTP_DUAL not recognized
140030: 09/04/24: Ruzica: Re: Modelsim GTP_DUAL not recognized
140032: 09/04/24: HT-Lab: Re: Modelsim GTP_DUAL not recognized
140033: 09/04/24: Ruzica: Re: Modelsim GTP_DUAL not recognized
140029: 09/04/24: <muthusnv@gmail.com>: FPGA evaluation board for SD/SDHC Host controller
140034: 09/04/24: LittleAlex: Re: FPGA evaluation board for SD/SDHC Host controller
140035: 09/04/24: Dave Pollum: Re: FPGA evaluation board for SD/SDHC Host controller
140130: 09/04/29: John Adair: Re: FPGA evaluation board for SD/SDHC Host controller
140222: 09/05/04: Sebastien @ Sundance: Re: FPGA evaluation board for SD/SDHC Host controller
140039: 09/04/24: russ: actel libero
140040: 09/04/25: whygee: Re: actel libero
140042: 09/04/24: russ: Re: actel libero
140043: 09/04/25: whygee: Re: actel libero
140051: 09/04/25: russ: Re: actel libero
140054: 09/04/25: Antti.Lukats@googlemail.com: Re: actel libero
140055: 09/04/25: Bert_Paris: Re: actel libero
140044: 09/04/24: Neil Steiner: About those TIEOFF primitives ...
140045: 09/04/25: glen herrmannsfeldt: Re: About those TIEOFF primitives ...
140046: 09/04/24: PrAsHaNtH@IIT: Error in Verilog Code
140047: 09/04/25: Jonathan Bromley: Re: Error in Verilog Code
140056: 09/04/26: <sbattazz@yahoo.co.jp>: Modelsim Actel Edition and Soft FIFO Controller
140057: 09/04/26: Bert_Paris: Re: Modelsim Actel Edition and Soft FIFO Controller
140061: 09/04/27: whygee: Re: Modelsim Actel Edition and Soft FIFO Controller
140063: 09/04/27: Bert_Paris: Re: Modelsim Actel Edition and Soft FIFO Controller
140066: 09/04/27: whygee: Re: Modelsim Actel Edition and Soft FIFO Controller
140059: 09/04/26: <sbattazz@yahoo.co.jp>: Re: Modelsim Actel Edition and Soft FIFO Controller
140134: 09/04/29: <sbattazz@yahoo.co.jp>: Re: Modelsim Actel Edition and Soft FIFO Controller
140143: 09/04/30: <sbattazz@yahoo.co.jp>: Re: Modelsim Actel Edition and Soft FIFO Controller
140058: 09/04/26: Antti: way to go Altera!
140060: 09/04/27: whygee: Re: way to go Altera!
140062: 09/04/26: Antti.Lukats@googlemail.com: Re: way to go Altera!
140079: 09/04/27: <kati.s.wright@gmail.com>: Re: way to go Altera!
140067: 09/04/27: <lolita.tangier@gmail.com>: ERROR: NgdBuild:604 - logical block
140070: 09/04/27: gabor: Re: ERROR: NgdBuild:604 - logical block
140073: 09/04/27: <lolita.tangier@gmail.com>: Re: ERROR: NgdBuild:604 - logical block
140082: 09/04/27: gabor: Re: ERROR: NgdBuild:604 - logical block
140123: 09/04/29: <lolita.tangier@gmail.com>: Re: ERROR: NgdBuild:604 - logical block
140124: 09/04/29: <lolita.tangier@gmail.com>: Re: ERROR: NgdBuild:604 - logical block
140157: 09/04/30: gabor: Re: ERROR: NgdBuild:604 - logical block
140388: 09/05/12: <lolita.tangier@gmail.com>: Re: ERROR: NgdBuild:604 - logical block
140068: 09/04/27: PrAsHaNtH@IIT: I have some doubts in verilog
140069: 09/04/27: glen herrmannsfeldt: Re: I have some doubts in verilog
140117: 09/04/29: glen herrmannsfeldt: Re: I have some doubts in verilog
140116: 09/04/28: Prashanth Kumar: Re: I have some doubts in verilog
140071: 09/04/27: yingqigang: virtex-4 questions
140072: 09/04/27: xdsd98123: FPGA/DSP/Video Board
140078: 09/04/27: Andy Peters: Re: FPGA/DSP/Video Board
140094: 09/04/28: Petter Gustad: Re: FPGA/DSP/Video Board
140100: 09/04/28: Petter Gustad: Re: FPGA/DSP/Video Board
140083: 09/04/27: gabor: Re: FPGA/DSP/Video Board
140086: 09/04/27: <ales.gorkic@gmail.com>: Re: FPGA/DSP/Video Board
140087: 09/04/27: cwoodring: Re: FPGA/DSP/Video Board
140118: 09/04/29: Petter Gustad: Re: FPGA/DSP/Video Board
140096: 09/04/28: Andy Peters: Re: FPGA/DSP/Video Board
140169: 09/05/01: Matrox Imaging: Re: FPGA/DSP/Video Board
140220: 09/05/04: Sebastien @ Sundance: Re: FPGA/DSP/Video Board
140074: 09/04/27: <oktem@su.sabanciuniv.edu>: hard macro basic clock reset question
140120: 09/04/29: Dirk Koch: Re: hard macro basic clock reset question
140077: 09/04/27: Antti: ISE 11.1 drops support for Virtex-2/Pro and Spartan-2/E
140084: 09/04/27: gabor: Re: ISE 11.1 drops support for Virtex-2/Pro and Spartan-2/E
140085: 09/04/27: <ales.gorkic@gmail.com>: Re: ISE 11.1 drops support for Virtex-2/Pro and Spartan-2/E
140088: 09/04/27: Antti.Lukats@googlemail.com: Re: ISE 11.1 drops support for Virtex-2/Pro and Spartan-2/E
140089: 09/04/28: aleksa: Re: ISE 11.1 drops support for Virtex-2/Pro and Spartan-2/E
140090: 09/04/28: Antti.Lukats@googlemail.com: Re: ISE 11.1 drops support for Virtex-2/Pro and Spartan-2/E
140095: 09/04/28: Andy Peters: Re: ISE 11.1 drops support for Virtex-2/Pro and Spartan-2/E
140097: 09/04/28: Antti.Lukats@googlemail.com: Re: ISE 11.1 drops support for Virtex-2/Pro and Spartan-2/E
140235: 09/05/05: Akhundov Jafar: ISE 11.1 won't work on Fedora 10 32bit
140091: 09/04/28: Uwe Bonnes: ISE 11.1 Webpack: How to install for Suse 64 Bits?
140092: 09/04/28: Uwe Bonnes: Re: ISE 11.1 Webpack: How to install for Suse 64 Bits?
140093: 09/04/28: Antti.Lukats@googlemail.com: Re: ISE 11.1 Webpack: How to install for Suse 64 Bits?
140098: 09/04/28: glen herrmannsfeldt: Re: ISE 11.1 Webpack: How to install for Suse 64 Bits?
140102: 09/04/28: Brian Drummond: Re: ISE 11.1 Webpack: How to install for Suse 64 Bits?
140121: 09/04/29: Uwe Bonnes: Re: ISE 11.1 Webpack: How to install for Suse 64 Bits?
140099: 09/04/28: jleslie48: a basics question: using input pins, pullup, short to ground vs
140103: 09/04/28: Jeff Cunningham: Re: a basics question: using input pins, pullup, short to ground
140110: 09/04/28: Muzaffer Kal: Re: a basics question: using input pins, pullup, short to ground vs driven signal.
140111: 09/04/28: Muzaffer Kal: Re: a basics question: using input pins, pullup, short to ground vs driven signal.
140115: 09/04/28: Muzaffer Kal: Re: a basics question: using input pins, pullup, short to ground vs driven signal.
140128: 09/04/29: MM: Re: a basics question: using input pins, pullup, short to ground vs driven signal.
140112: 09/04/29: glen herrmannsfeldt: Re: a basics question: using input pins, pullup, short to ground vs ?driven signal.
140122: 09/04/29: Brian Drummond: Re: a basics question: using input pins, pullup, short to ground vs driven signal.
140144: 09/04/30: Martin Thompson: Re: a basics question: using input pins, pullup, short to ground vs driven signal.
140150: 09/04/30: MM: Re: a basics question: using input pins, pullup, short to ground vs driven signal.
140104: 09/04/28: jleslie48: Re: a basics question: using input pins, pullup, short to ground vs
140105: 09/04/28: jleslie48: Re: a basics question: using input pins, pullup, short to ground vs
140106: 09/04/28: jleslie48: Re: a basics question: using input pins, pullup, short to ground vs
140107: 09/04/28: jleslie48: Re: a basics question: using input pins, pullup, short to ground vs
140108: 09/04/28: jleslie48: Re: a basics question: using input pins, pullup, short to ground vs
140109: 09/04/28: jleslie48: Re: a basics question: using input pins, pullup, short to ground vs
140113: 09/04/28: jleslie48: Re: a basics question: using input pins, pullup, short to ground vs
140114: 09/04/28: jleslie48: Re: a basics question: using input pins, pullup, short to ground vs
140101: 09/04/28: MM: ISE11.1 environment variables mess
140125: 09/04/29: <metinnn@gmx.de>: offset out
140149: 09/04/30: <padudle@gmail.com>: Re: offset out
140168: 09/05/01: MM: Re: offset out
140179: 09/05/01: MM: Re: offset out
140163: 09/05/01: <metinnn@gmx.de>: Re: offset out
140177: 09/05/01: <metinnn@gmx.de>: Re: offset out
140199: 09/05/02: <metinnn@gmx.de>: Re: offset out
140126: 09/04/29: jacko: Quartus Timing
140131: 09/04/29: Muzaffer Kal: Re: Quartus Timing
140132: 09/04/29: Mike Treseler: Re: Quartus Timing
140152: 09/04/30: Mike Treseler: Re: Quartus Timing
140172: 09/05/01: Mike Treseler: Re: Quartus Timing
140135: 09/04/29: Jacko: Re: Quartus Timing
140158: 09/04/30: Jacko: Re: Quartus Timing
140127: 09/04/29: David Fejes: prohibit global clock designation
140140: 09/04/29: <goouse@twinmail.de>: Re: prohibit global clock designation
140153: 09/04/30: LittleAlex: Re: prohibit global clock designation
140165: 09/05/01: David Fejes: Re: prohibit global clock designation
140129: 09/04/29: <jetmarc@hotmail.com>: ASIC from working FPGA design
140133: 09/04/29: Muzaffer Kal: Re: ASIC from working FPGA design
140137: 09/04/30: Petter Gustad: Re: ASIC from working FPGA design
140139: 09/04/30: Kim Enkovaara: Re: ASIC from working FPGA design
140146: 09/04/30: <jon@beniston.com>: Re: ASIC from working FPGA design
140138: 09/04/29: JSreeniv: Representation of Read processor convention
140167: 09/05/01: Jonathan Bromley: Re: Representation of Read processor convention
140142: 09/04/30: <1stderivative@gmail.com>: FPGA simulator for face recognition
140145: 09/04/30: Martin Thompson: Re: FPGA simulator for face recognition
140154: 09/04/30: glen herrmannsfeldt: Re: FPGA simulator for face recognition
140147: 09/04/30: redpumice: Re: FPGA simulator for face recognition
140148: 09/04/30: <1stderivative@gmail.com>: Re: FPGA simulator for face recognition
140151: 09/04/30: <jprovidenza@yahoo.com>: Re: FPGA simulator for face recognition
140159: 09/04/30: mng: Re: FPGA simulator for face recognition
140155: 09/04/30: Mawa_fugo: Xilinx ground pin
140156: 09/04/30: MM: Re: Xilinx ground pin
140166: 09/05/01: halong: Re: Xilinx ground pin
140160: 09/04/30: MM: ISE/EDK/SDK 11.1 licensing
140161: 09/04/30: Antti.Lukats@googlemail.com: Re: ISE/EDK/SDK 11.1 licensing
140162: 09/05/01: MikeWhy: Re: ISE/EDK/SDK 11.1 licensing
140170: 09/05/01: MM: Re: ISE/EDK/SDK 11.1 licensing
140171: 09/05/01: MM: Re: ISE/EDK/SDK 11.1 licensing
140181: 09/05/01: StoneThrower: Re: ISE/EDK/SDK 11.1 licensing
140183: 09/05/01: Ed McGettigan: Re: ISE/EDK/SDK 11.1 licensing
140188: 09/05/02: Sean Durkin: Re: ISE/EDK/SDK 11.1 licensing
140210: 09/05/04: Sean Durkin: Re: ISE/EDK/SDK 11.1 licensing
140187: 09/05/02: Sean Durkin: Re: ISE/EDK/SDK 11.1 licensing
140208: 09/05/04: Sean Durkin: Re: ISE/EDK/SDK 11.1 licensing
140173: 09/05/01: MikeWhy: Re: ISE/EDK/SDK 11.1 licensing
140174: 09/05/01: MM: Re: ISE/EDK/SDK 11.1 licensing
140182: 09/05/01: MikeWhy: Re: ISE/EDK/SDK 11.1 licensing
140164: 09/05/01: Antti.Lukats@googlemail.com: Re: ISE/EDK/SDK 11.1 licensing
140175: 09/05/01: LittleAlex: Re: ISE/EDK/SDK 11.1 licensing
140176: 09/05/01: <no_spa2005@yahoo.fr>: Re: ISE/EDK/SDK 11.1 licensing
140178: 09/05/01: LittleAlex: Re: ISE/EDK/SDK 11.1 licensing
140180: 09/05/01: Andy Peters: Re: ISE/EDK/SDK 11.1 licensing
140186: 09/05/01: Antti.Lukats@googlemail.com: Re: ISE/EDK/SDK 11.1 licensing

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