88947: 05/09/01: Ram: FS: Lot of 60 XCV1000 FPGAs
88968: 05/09/01: Vladislav Muravin: Re: Lot of 60 XCV1000 FPGAs
88978: 05/09/01: Ram: Re: Lot of 60 XCV1000 FPGAs
88982: 05/09/01: Ray Andraka: Re: Lot of 60 XCV1000 FPGAs
89028: 05/09/02: John Adair: Re: Lot of 60 XCV1000 FPGAs
88952: 05/09/01: ciappalastringa: Mentor FPGA Advantage, a simple question
88974: 05/09/01: Mike Treseler: Re: Mentor FPGA Advantage, a simple question
89074: 05/09/05: ciappalastringa: Re: Mentor FPGA Advantage, a simple question
88953: 05/09/01: <giachella.g@laben.it>: Discrepancies in area estimation (Precision RTL vs Xilinx ISE Map)
88965: 05/09/01: Aurelian Lazarut: Re: Discrepancies in area estimation (Precision RTL vs Xilinx ISE
88955: 05/09/01: <denizdikmen@gmail.com>: CPLD CoolRunner-II - IO current limited to 8mA?
88958: 05/09/01: Aurelian Lazarut: Re: CPLD CoolRunner-II - IO current limited to 8mA?
89012: 05/09/02: Falk Brunner: Re: CPLD CoolRunner-II - IO current limited to 8mA?
89026: 05/09/02: John Adair: Re: CPLD CoolRunner-II - IO current limited to 8mA?
89030: 05/09/03: Jim Granville: Re: CPLD CoolRunner-II - IO current limited to 8mA?
88956: 05/09/01: Dix: bare die (non packaged) FPGA, CPLD, controllers ?
88986: 05/09/01: Daniel Leu: Re: bare die (non packaged) FPGA, CPLD, controllers ?
89072: 05/09/05: Dix: Re: bare die (non packaged) FPGA, CPLD, controllers ?
89087: 05/09/05: Jon Beniston: Re: bare die (non packaged) FPGA, CPLD, controllers ?
89178: 05/09/07: Dix: Re: bare die (non packaged) FPGA, CPLD, controllers ?
88957: 05/09/01: Marco: A strange behavior
88977: 05/09/01: John_H: Re: A strange behavior
88989: 05/09/02: Marco: Re: A strange behavior
88959: 05/09/01: Ian Muncaster: New FPGA development board.
88960: 05/09/01: Martin: "Perform Timing-Driven Packing and Placement" error?
88961: 05/09/01: Ben Jones: Re: "Perform Timing-Driven Packing and Placement" error?
88983: 05/09/01: Ray Andraka: Re: "Perform Timing-Driven Packing and Placement" error?
88994: 05/09/02: Martin: Re: "Perform Timing-Driven Packing and Placement" error?
88996: 05/09/02: Martin: Re: "Perform Timing-Driven Packing and Placement" error?
88963: 05/09/01: zoinks@mytrashmail.com: Using the XUP Virtex-II Pro with EDK 6.3 => errors during platform level signal connect.
88966: 05/09/01: Paul Hartke: Re: Using the XUP Virtex-II Pro with EDK 6.3 => errors during platform
88998: 05/09/02: zoinks@mytrashmail.com: Re: Using the XUP Virtex-II Pro with EDK 6.3 => errors during platform level signal connect.
88964: 05/09/01: abeaujean@gillam-fei.be: Strange behaviour while trying to program MAX II CPLD's
89144: 05/09/06: Paul Leventis (at home): Re: Strange behaviour while trying to program MAX II CPLD's
88967: 05/09/01: huangjie: Spartan3 PCI SSO(Simultaneously Switching Output) problem
88976: 05/09/01: John_H: Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem
89001: 05/09/02: Austin Lesea: Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem
89009: 05/09/02: John_H: Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem
89016: 05/09/02: Austin Lesea: Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem
89029: 05/09/03: John_H: Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem
88991: 05/09/02: huangjie: Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem
89015: 05/09/02: huangjie: Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem
89106: 05/09/05: huangjie: Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem
89109: 05/09/05: huangjie: Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem
89110: 05/09/05: huangjie: Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem
89116: 05/09/06: dfx: Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem
88970: 05/09/01: JTW: MicroBlaze: PLX PCI 9056 IP
88971: 05/09/01: John Larkin: current!
88975: 05/09/01: John_H: Re: current!
88985: 05/09/01: John Larkin: Re: current!
89004: 05/09/02: John_H: Re: current!
88972: 05/09/01: TD: Xilinx Virtex II fpga - providing single ended signal to lvds defined pin
88973: 05/09/01: Matthew Plante: FIFO PhysDesignRules:993
88979: 05/09/01: Philip Pemberton: Modelsim XE and multi-file Verilog projects
88984: 05/09/01: TD: Re: Modelsim XE and multi-file Verilog projects
89107: 05/09/05: Marko: Re: Modelsim XE and multi-file Verilog projects
89130: 05/09/06: gallen: Re: Modelsim XE and multi-file Verilog projects
89134: 05/09/06: johnp: Re: Modelsim XE and multi-file Verilog projects
88980: 05/09/01: Gabor: Xilinx and Lattice tools on one machine?
89958: 05/09/30: <troy.scott@latticesemi.com>: Re: Xilinx and Lattice tools on one machine?
89979: 05/09/30: Gabor: Re: Xilinx and Lattice tools on one machine?
88987: 05/09/01: <praveen.kantharajapura@gmail.com>: I2C "SCL" line problem
88995: 05/09/02: <alan@nishioka.com>: Re: I2C "SCL" line problem
89013: 05/09/02: Falk Brunner: Re: I2C "SCL" line problem
89075: 05/09/05: Jim Granville: Re: I2C "SCL" line problem
89097: 05/09/05: John_H: Re: I2C "SCL" line problem
89065: 05/09/04: Brad Smallridge: Re: I2C "SCL" line problem
89070: 05/09/04: <praveen.kantharajapura@gmail.com>: Re: I2C "SCL" line problem
88990: 05/09/02: Gra: OT: CPLD - SimuCAD S/W CD
89003: 05/09/02: John_H: Re: CPLD - SimuCAD S/W CD
89031: 05/09/03: Grahame Kelly: Re: CPLD - SimuCAD S/W CD
89034: 05/09/03: Antonio Pasini: Re: CPLD - SimuCAD S/W CD
89008: 05/09/02: gallen: Re: CPLD - SimuCAD S/W CD
88992: 05/09/02: Kris Heyrman: Followup: USB cable, Xilinx XUP, EDK/ISE 7.1, Fedora Core 3
89350: 05/09/13: S.T.: Re: Followup: USB cable, Xilinx XUP, EDK/ISE 7.1, Fedora Core 3
89358: 05/09/13: Paul Hartke: Re: Followup: USB cable, Xilinx XUP, EDK/ISE 7.1, Fedora Core 3
89443: 05/09/15: S.T.: Re: Followup: USB cable, Xilinx XUP, EDK/ISE 7.1, Fedora Core 3
88997: 05/09/02: vssumesh: Multidimensional port.
89002: 05/09/02: John_H: Re: Multidimensional port.
89006: 05/09/02: vssumesh: Re: Multidimensional port.
89011: 05/09/02: <allanherriman@hotmail.com>: Re: Multidimensional port.
89000: 05/09/02: Marco: Modelsim simulation question
89005: 05/09/02: zoinks@mytrashmail.com: XUP Virtex-II Pro "invalid target architecture"
89010: 05/09/02: Paul Hartke: Re: XUP Virtex-II Pro "invalid target architecture"
89038: 05/09/03: Alex Gibson: Re: XUP Virtex-II Pro "invalid target architecture"
89129: 05/09/06: Alex Gibson: Re: XUP Virtex-II Pro "invalid target architecture"
89083: 05/09/05: zoinks@mytrashmail.com: Re: XUP Virtex-II Pro "invalid target architecture"
89084: 05/09/05: zoinks@mytrashmail.com: Re: XUP Virtex-II Pro "invalid target architecture"
89101: 05/09/05: Paul Hartke: Re: XUP Virtex-II Pro "invalid target architecture"
89344: 05/09/13: zoinks@mytrashmail.com: Re: XUP Virtex-II Pro "invalid target architecture"
89359: 05/09/13: Paul Hartke: Re: XUP Virtex-II Pro "invalid target architecture"
89447: 05/09/15: zoinks@mytrashmail.com: Re: XUP Virtex-II Pro "invalid target architecture"
89007: 05/09/02: vssumesh: Creating higher bit multipliers from low bit.
89022: 05/09/02: Ray Andraka: Re: Creating higher bit multipliers from low bit.
89048: 05/09/03: Richard Carey: Re: Creating higher bit multipliers from low bit.
89018: 05/09/02: Marc Battyani: SI considerations for single chip memory configurations
89041: 05/09/03: John_H: Re: SI considerations for single chip memory configurations
89019: 05/09/02: Lathe_Biosas: gal16v8 CUPL problems
89024: 05/09/03: Jim Granville: Re: gal16v8 CUPL problems
89021: 05/09/02: <amir.intisar@gmail.com>: Spartan 3 Ram Instantiation
89035: 05/09/03: Falk Brunner: Re: Spartan 3 Ram Instantiation
89040: 05/09/03: John_H: Re: Spartan 3 Ram Instantiation
89062: 05/09/04: Philip Freidin: Re: Spartan 3 Ram Instantiation
89096: 05/09/05: John_H: Re: Spartan 3 Ram Instantiation
89231: 05/09/08: John_H: Re: Spartan 3 Ram Instantiation
89061: 05/09/04: <amir.intisar@gmail.com>: Re: Spartan 3 Ram Instantiation
89064: 05/09/04: Brad Smallridge: Re: Spartan 3 Ram Instantiation
89176: 05/09/07: <amir.intisar@gmail.com>: Re: Spartan 3 Ram Instantiation
89025: 05/09/02: Roger: Platform Cable USB
89033: 05/09/03: James Horn: Re: Platform Cable USB
89079: 05/09/05: Roger: Re: Platform Cable USB
89036: 05/09/03: Marco: The best way to sum 8 datas?
89037: 05/09/03: Slurp: Re: The best way to sum 8 datas?
89056: 05/09/04: Marco: Re: The best way to sum 8 datas?
89039: 05/09/03: Philip Pemberton: Modelling latches in Verilog
89047: 05/09/03: mk: Re: Modelling latches in Verilog
89053: 05/09/04: Philip Pemberton: Re: Modelling latches in Verilog
89042: 05/09/03: Mak: High baud rate chips for RS232 protocol
89044: 05/09/03: Falk Brunner: Re: High baud rate chips for RS232 protocol
89045: 05/09/03: Slurp: Re: High baud rate chips for RS232 protocol
89046: 05/09/04: Jim Granville: Re: High baud rate chips for RS232 protocol
89076: 05/09/05: Simon Peacock: Re: High baud rate chips for RS232 protocol
89063: 05/09/04: <langwadt@ieee.org>: Re: High baud rate chips for RS232 protocol
89123: 05/09/06: Rene Tschaggelar: Re: High baud rate chips for RS232 protocol
89043: 05/09/03: Gary Pace: Long Multiplication
89049: 05/09/03: Symon: Re: Long Multiplication
89050: 05/09/04: Gary Pace: Re: Long Multiplication
89051: 05/09/03: <cell_rx@msn.com>: IC design contract
89052: 05/09/03: Kumar: Logic??
89054: 05/09/04: <vizziee@gmail.com>: Re: Logic??
89059: 05/09/04: Slurp: Re: Logic??
89058: 05/09/04: Kumar: Re: Logic??
89060: 05/09/04: John_H: Re: Logic??
89082: 05/09/05: Aurelian Lazarut: Re: Logic??
89223: 05/09/08: Kumar: Re: Logic??
89055: 05/09/04: Michael: Partial Reconfiguration : New Forum
89057: 05/09/04: Paul Hartke: Re: Partial Reconfiguration : New Forum
89066: 05/09/04: <VAX9000@gmail.com>: Quartus web edition simulation with off-chip logic?
89067: 05/09/04: Narayan: Problem with interfacingT-VPACK with ALTERA QUIP5.0
89073: 05/09/05: raj: Re: Problem with interfacingT-VPACK with ALTERA QUIP5.0
89085: 05/09/05: xvhdl: Re: Problem with interfacingT-VPACK with ALTERA QUIP5.0
89086: 05/09/05: xvhdl: Re: Problem with interfacingT-VPACK with ALTERA QUIP5.0
89090: 05/09/05: Narayan: Re: Problem with interfacingT-VPACK with ALTERA QUIP5.0
89068: 05/09/04: AdamS: coe file of Xilinx MAC FIR core??
89071: 05/09/05: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?=: Re: coe file of Xilinx MAC FIR core??
89069: 05/09/04: CODE_IS_BAD: Reading internal signals through a testbench.
89078: 05/09/05: <ALuPin@web.de>: Re: Reading internal signals through a testbench.
89104: 05/09/05: Jeff Cunningham: Re: Reading internal signals through a testbench.
89103: 05/09/05: Andrew FPGA: Re: Reading internal signals through a testbench.
89150: 05/09/06: Gabor: Re: Reading internal signals through a testbench.
89077: 05/09/05: abeaujean@gillam-fei.be: Reprogramming one MAXII EPM1270 vs security bit set
89141: 05/09/06: Luis Cupido: Re: Reprogramming one MAXII EPM1270 vs security bit set
89316: 05/09/12: <joe.delaere@gmail.com>: Re: Reprogramming one MAXII EPM1270 vs security bit set
89080: 05/09/05: Sylvain Munaut: Defining Environment variables inside EDK
89157: 05/09/06: Amit Kasat: Re: Defining Environment variables inside EDK
89180: 05/09/07: Sylvain Munaut: Re: Defining Environment variables inside EDK
89081: 05/09/05: Paul Boven: Fastest input IOB on a Spartan-3?
89191: 05/09/07: Symon: Re: Fastest input IOB on a Spartan-3?
89192: 05/09/07: Austin Lesea: Re: Fastest input IOB on a Spartan-3?
89201: 05/09/07: Symon: Re: Fastest input IOB on a Spartan-3?
89207: 05/09/07: Austin Lesea: Re: Fastest input IOB on a Spartan-3?
89210: 05/09/07: Symon: Re: Fastest input IOB on a Spartan-3?
89211: 05/09/07: austin: Re: Fastest input IOB on a Spartan-3?
89284: 05/09/10: austin: Re: Fastest input IOB on a Spartan-3?
89258: 05/09/09: Brian Davis: Re: Fastest input IOB on a Spartan-3?
89088: 05/09/05: Gromer: Nand Flash Emulator
89089: 05/09/05: Sebastian Schmidt: False values in Quartus In-System Memory Editor
89091: 05/09/05: <ALuPin@web.de>: Re: False values in Quartus In-System Memory Editor
89093: 05/09/05: Sebastian Schmidt: Re: False values in Quartus In-System Memory Editor
89124: 05/09/06: Sebastian Schmidt: Re: False values in Quartus In-System Memory Editor
89133: 05/09/06: Sebastian Schmidt: Re: False values in Quartus In-System Memory Editor
89113: 05/09/05: <ALuPin@web.de>: Re: False values in Quartus In-System Memory Editor
89126: 05/09/06: <ALuPin@web.de>: Re: False values in Quartus In-System Memory Editor
89092: 05/09/05: I. Ulises Hernandez: PPC405 32 bit aligned accesses
89094: 05/09/05: Symon: Re: PPC405 32 bit aligned accesses
89095: 05/09/05: I. Ulises Hernandez: Re: PPC405 32 bit aligned accesses
89100: 05/09/05: Symon: Re: PPC405 32 bit aligned accesses
89102: 05/09/05: Kolja Sulimma: Re: PPC405 32 bit aligned accesses
89114: 05/09/06: I. Ulises Hernandez: Re: PPC405 32 bit aligned accesses
89138: 05/09/06: Peter Ryser: Re: PPC405 32 bit aligned accesses
89142: 05/09/06: I. Ulises Hernandez: Re: PPC405 32 bit aligned accesses
89146: 05/09/06: Symon: Re: PPC405 32 bit aligned accesses
89158: 05/09/06: Peter Ryser: Re: PPC405 32 bit aligned accesses
89160: 05/09/06: Symon: Re: PPC405 32 bit aligned accesses
89163: 05/09/06: Peter Ryser: Re: PPC405 32 bit aligned accesses
89167: 05/09/07: I. Ulises Hernandez: Re: PPC405 32 bit aligned accesses
89187: 05/09/07: Symon: Re: PPC405 32 bit aligned accesses
89234: 05/09/08: Peter Ryser: Re: PPC405 32 bit aligned accesses
89098: 05/09/05: <skatoulas@hotmail.com>: Area Estimation Issues
89099: 05/09/05: VSP: Strange warning "WARNING:MapLib:701 - Signal P_GPIO_3 connected to top level port P_GPIO_3 has been removed."
89111: 05/09/06: Zara: Re: Strange warning "WARNING:MapLib:701 - Signal P_GPIO_3 connected
89137: 05/09/06: Duane Clark: Re: Strange warning "WARNING:MapLib:701 - Signal P_GPIO_3 connected
89108: 05/09/05: Andre G.: Quartus2 WEB: Simulating from test bench. Is that possible?
89112: 05/09/05: <ALuPin@web.de>: Re: Quartus2 WEB: Simulating from test bench. Is that possible?
89117: 05/09/06: <ALuPin@web.de>: Re: Quartus2 WEB: Simulating from test bench. Is that possible?
89115: 05/09/06: mehul: Carry saver adder
89118: 05/09/06: vssumesh: Disconnect the FPGA I/O pads from the outside world
89173: 05/09/07: pipjockey: Re: Disconnect the FPGA I/O pads from the outside world
89268: 05/09/09: Matthieu Michon: Re: Disconnect the FPGA I/O pads from the outside world
89212: 05/09/07: vssumesh: Re: Disconnect the FPGA I/O pads from the outside world
89246: 05/09/08: vssumesh: Re: Disconnect the FPGA I/O pads from the outside world
89251: 05/09/09: dfx: Re: Disconnect the FPGA I/O pads from the outside world
89119: 05/09/06: amko: SPARATAN 2E - input clock
89122: 05/09/06: I. Ulises Hernandez: Re: SPARATAN 2E - input clock
89120: 05/09/06: Sven Gowal: PCI on ML310 Xilinx board
89140: 05/09/06: Peter Ryser: Re: PCI on ML310 Xilinx board
89149: 05/09/06: Sven Gowal: Re: PCI on ML310 Xilinx board
89215: 05/09/07: Paul Hartke: Re: PCI on ML310 Xilinx board
89219: 05/09/08: Sven Gowal: Re: PCI on ML310 Xilinx board
89121: 05/09/06: Sima: Spartan 3E and Spartan 3 with GTL
89125: 05/09/06: Newman: Partial vector range in instance warning
89135: 05/09/06: Newman: Re: Partial vector range in instance warning
89127: 05/09/06: Herman Roebbers: Final Call for Participants CPA 2005 (18-21 Sept 2005) in Eindhoven
89128: 05/09/06: blah: SI newsgroup
89131: 05/09/06: MM: Re: SI newsgroup
89132: 05/09/06: Paul Leventis (at home): ANN: Altera Power Net Seminar #2
89147: 05/09/06: Paul Leventis (at home): Re: Altera Power Net Seminar #2
89156: 05/09/06: che_fong: Re: Altera Power Net Seminar #2
89136: 05/09/06: Andrew Greensted: Any GOSPL Docs?
89139: 05/09/06: Luis Cupido: Cyclone conf flash - 25p10 !
89161: 05/09/07: Al Clark: Re: Cyclone conf flash - 25p10 !
89164: 05/09/07: Jim Granville: Re: Cyclone conf flash - 25p10 !
89181: 05/09/07: Luis Cupido: Re: Cyclone conf flash - 25p10 !
89197: 05/09/08: Jim Granville: Re: Cyclone conf flash - 25p10 !
89238: 05/09/09: Jim Granville: Re: Cyclone conf flash - 25p10 !
89244: 05/09/09: Mark McDougall: Re: Cyclone conf flash - 25p10 !
89247: 05/09/09: Al Clark: Re: Cyclone conf flash - 25p10 !
89252: 05/09/09: Mark McDougall: Re: Cyclone conf flash - 25p10 !
89249: 05/09/09: Al Clark: Re: Cyclone conf flash - 25p10 !
89260: 05/09/09: Al Clark: Re: Cyclone conf flash - 25p10 !
89267: 05/09/09: Nial Stewart: Re: Cyclone conf flash - 25p10 !
89276: 05/09/10: Luis Cupido: Re: Cyclone conf flash - 25p10 !
89190: 05/09/07: Luis Cupido: Re: Cyclone conf flash - 25p10 !
89179: 05/09/07: Luis Cupido: Re: Cyclone conf flash - 25p10 !
89177: 05/09/07: jai.dhar@gmail.com: Re: Cyclone conf flash - 25p10 !
89227: 05/09/08: jai.dhar@gmail.com: Re: Cyclone conf flash - 25p10 !
89248: 05/09/08: jai.dhar@gmail.com: Re: Cyclone conf flash - 25p10 !
89259: 05/09/09: jai.dhar@gmail.com: Re: Cyclone conf flash - 25p10 !
89271: 05/09/09: jai.dhar@gmail.com: Re: Cyclone conf flash - 25p10 !
89143: 05/09/06: Brad Smallridge: WARNING:HDLParsers:3481 - No primary, secondary unit in the file
89145: 05/09/06: Paul Leventis (at home): Re: Low Power RTL Design
89148: 05/09/06: Herman Roebbers: Final Call for Participants & fringe CPA 2005 (18-21 Sept 2005) in Eindhoven
89151: 05/09/06: CMOS: spartan 3 starter kit auto configuration at power up
89152: 05/09/06: Brad Smallridge: Re: spartan 3 starter kit auto configuration at power up
89175: 05/09/07: Marco: Re: spartan 3 starter kit auto configuration at power up
89153: 05/09/06: Eric: Linux on Viretex-II pro
89155: 05/09/06: Peter Ryser: Re: Linux on Viretex-II pro
89154: 05/09/06: Eric Smith: Spartan-3E Starter Kit availability slips to December
89170: 05/09/07: Mike Harrison: Re: Spartan-3E Starter Kit availability slips to December
89195: 05/09/07: Mike Treseler: Re: Spartan-3E Starter Kit availability slips to December
89199: 05/09/07: Duane Clark: Re: Spartan-3E Starter Kit availability slips to December
89216: 05/09/08: Phil Tomson: Re: Spartan-3E Starter Kit availability slips to December
89183: 05/09/08: Alex Gibson: Re: Spartan-3E Starter Kit availability slips to December
89193: 05/09/07: jcarr@linuxmachines.com: Re: Spartan-3E Starter Kit availability slips to December
89162: 05/09/07: news.green.ch: Signed addition
89171: 05/09/07: Sylvain Munaut: Re: Signed addition
89172: 05/09/07: Simon Peacock: Re: Signed addition
89174: 05/09/07: Sylvain Munaut: Re: Signed addition
89218: 05/09/08: Peter Harrison: Re: Signed addition
89257: 05/09/10: Simon Peacock: Re: Signed addition
89206: 05/09/07: Paulo Dutra: Re: Signed addition
89265: 05/09/09: Marko: Re: Signed addition
89288: 05/09/11: Simon Peacock: Re: Signed addition
89165: 05/09/06: Lina: to use flash on the fpga board
89213: 05/09/07: Lina: Re: to use flash on the fpga board
89166: 05/09/07: <jamilkhatib75@yahoo.com>: OpenTech open source designs and tools
89168: 05/09/07: logjam: Help finding Signetics Datasheets
89198: 05/09/07: logjam: Re: Help finding Signetics Datasheets
89169: 05/09/07: Tony30: used boards? cache design? DDR2 controller?
89182: 05/09/07: Matthew Plante: ISE 64bit question
89185: 05/09/07: <aholtzma@gmail.com>: Re: ISE 64bit question
89186: 05/09/07: Hiding in Plain Sight: Re: ISE 64bit question
89228: 05/09/08: mk: Re: ISE 64bit question
89188: 05/09/07: Gardovan: chipscope/core implementation
89194: 05/09/07: Tim Verstraete: ISE7.1 SP4: proble and chipscope problem
89200: 05/09/07: Duane Clark: Re: ISE7.1 SP4: proble and chipscope problem
89196: 05/09/07: Roger: RocketIO code example
89202: 05/09/07: Duane Clark: Re: RocketIO code example
89203: 05/09/07: Roger: Re: RocketIO code example
89214: 05/09/07: Designfreek: pll
89220: 05/09/08: <nahum_barnea@yahoo.com>: burn xcf16p through PCI jtag
89221: 05/09/08: Newman: Re: to use flash on the fpga board
89222: 05/09/08: <henrique.portela@gmail.com>: ML361 Documentation....
89224: 05/09/08: Ben Jones: Re: ML361 Documentation....
89225: 05/09/08: <henrique.portela@gmail.com>: Re: ML361 Documentation....
89226: 05/09/08: Tim Verstraete: [XST] FSM extraction question
89229: 05/09/08: Tim Verstraete: Re: FSM extraction question
89240: 05/09/08: Mike Treseler: Re: [XST] FSM extraction question
89250: 05/09/09: <ALuPin@web.de>: Re: FSM extraction question
89230: 05/09/08: mike: xilinx virtex 2 multimedia board ( XC2V2000)
89232: 05/09/08: <sanjay.gajendra@gmail.com>: Quartus II - Timing Analyzer
89245: 05/09/09: Mark McDougall: Re: Quartus II - Timing Analyzer
89269: 05/09/09: Subroto Datta: Re: Quartus II - Timing Analyzer
89233: 05/09/08: Pete Fraser: digilent web site?
89236: 05/09/08: Paul Hartke: Re: digilent web site?
89237: 05/09/08: Zara: Microblaze and LMB
89241: 05/09/08: Paul Hartke: Re: Microblaze and LMB
89253: 05/09/09: Zara: Re: Microblaze and LMB
89239: 05/09/08: Nitesh: EDK 7.1 simulation
89242: 05/09/08: archilleswaterland@hotmail.com: Timing Violation Quartus "__Z" issue
89243: 05/09/08: logjam: Reading a PAL fusemap with a microscope
89277: 05/09/09: logjam: Re: Reading a PAL fusemap with a microscope
89360: 05/09/13: Marc Reinig: Re: Reading a PAL fusemap with a microscope
89366: 05/09/14: Jim Granville: Re: Reading a PAL fusemap with a microscope
89519: 05/09/17: Philip Freidin: Re: Reading a PAL fusemap with a microscope
89528: 05/09/17: Alex Freed: Re: Reading a PAL fusemap with a microscope
89540: 05/09/19: Jim Granville: Re: Reading a PAL fusemap with a microscope
89555: 05/09/19: Ram: Re: Reading a PAL fusemap with a microscope
89574: 05/09/19: Alex Freed: Re: Reading a PAL fusemap with a microscope
90044: 05/10/03: Retro: Re: Reading a PAL fusemap with a microscope
89293: 05/09/11: logjam: Re: Reading a PAL fusemap with a microscope
89331: 05/09/12: logjam: Re: Reading a PAL fusemap with a microscope
89355: 05/09/13: Gabor: Re: Reading a PAL fusemap with a microscope
89511: 05/09/16: logjam: Re: Reading a PAL fusemap with a microscope
89522: 05/09/17: logjam: Re: Reading a PAL fusemap with a microscope
89538: 05/09/18: logjam: Re: Reading a PAL fusemap with a microscope
89539: 05/09/18: logjam: Re: Reading a PAL fusemap with a microscope
89254: 05/09/09: Giox: Post synthesis simulation errors
89262: 05/09/09: Mike Treseler: Re: Post synthesis simulation errors
89263: 05/09/09: johnp: Re: Post synthesis simulation errors
89264: 05/09/09: Phil Hays: Re: Post synthesis simulation errors
89315: 05/09/12: Phil Hays: Re: Post synthesis simulation errors
89300: 05/09/12: Giox: Re: Post synthesis simulation errors
89341: 05/09/13: Pasacco: Re: Post synthesis simulation errors
89352: 05/09/13: Giox: Re: Post synthesis simulation errors
89353: 05/09/13: Giox: Re: Post synthesis simulation errors
89255: 05/09/09: Robert: Has anyone successfully used opencores PCI in FPGA desings?
89283: 05/09/10: Kevin Brace: Re: Has anyone successfully used opencores PCI in FPGA desings?
89292: 05/09/12: Mark McDougall: Re: Has anyone successfully used opencores PCI in FPGA desings?
89311: 05/09/12: John McCaskill: Re: Has anyone successfully used opencores PCI in FPGA desings?
89256: 05/09/09: <stud_lang_jap@yahoo.com>: implementing the tristate bus
89261: 05/09/09: Vladislav Muravin: Re: implementing the tristate bus
89275: 05/09/09: <stud_lang_jap@yahoo.com>: Re: implementing the tristate bus
89278: 05/09/09: vssumesh: Re: implementing the tristate bus
89266: 05/09/09: Nitesh: compedklib error
89270: 05/09/09: Bob Myers: Need advice: old Xilinx schematic design -> VHDL...GSR issue(s)
89280: 05/09/09: Mike Treseler: Re: Need advice: old Xilinx schematic design -> VHDL...GSR issue(s)
89290: 05/09/11: Duane Clark: Re: Need advice: old Xilinx schematic design -> VHDL...GSR issue(s)
89301: 05/09/12: Bob Myers: Re: Need advice: old Xilinx schematic design -> VHDL...GSR issue(s)
89468: 05/09/15: Bob Myers: Re: Need advice: old Xilinx schematic design -> VHDL...GSR issue(s)
89272: 05/09/09: arincm@hotmail.com: creating a custom opb bus master
89273: 05/09/09: <alan@nishioka.com>: Re: creating a custom opb bus master
89282: 05/09/10: Paul Hartke: Re: creating a custom opb bus master
89286: 05/09/10: beeraka@gmail.com: Re: creating a custom opb bus master
89281: 05/09/09: Adam Megacz: future of antifuse fpgas?
89285: 05/09/10: austin: Re: future of antifuse fpgas?
89294: 05/09/11: Adam Megacz: Re: future of antifuse fpgas?
89309: 05/09/12: Philip Freidin: Re: future of antifuse fpgas?
89530: 05/09/18: rk: Re: future of antifuse fpgas?
89531: 05/09/18: austin: Re: future of antifuse fpgas?
89534: 05/09/18: rk: Re: future of antifuse fpgas?
89312: 05/09/12: Thomas Womack: Re: future of antifuse fpgas?
89335: 05/09/12: Adam Megacz: Re: future of antifuse fpgas?
89287: 05/09/11: Ram: Which JTAG cable for Xilinx & Linux?
89289: 05/09/12: Grahame Kelly: Re: Which JTAG cable for Xilinx & Linux?
89324: 05/09/12: Neil Glenn Jacobson: Re: Which JTAG cable for Xilinx & Linux?
89332: 05/09/13: Zara: Re: Which JTAG cable for Xilinx & Linux?
89291: 05/09/11: <ni.neofpga@gmail.com>: Block RAM problem (spartan 3)
89295: 05/09/12: Stephane: several ucf files?
89345: 05/09/13: <allanherriman@hotmail.com>: Re: several ucf files?
89296: 05/09/12: Jon Schneider: SDRAM quality
89305: 05/09/12: Hiding in Plain Sight: Re: SDRAM quality
89307: 05/09/12: Aurelian Lazarut: Re: SDRAM quality
89306: 05/09/12: Mike Harrison: Re: SDRAM quality
89326: 05/09/13: Mark McDougall: Re: SDRAM quality
89378: 05/09/14: Mark McDougall: Re: SDRAM quality
89356: 05/09/13: jai.dhar@gmail.com: Re: SDRAM quality
89453: 05/09/15: Alvin Andries: Re: SDRAM quality
89467: 05/09/15: Mike Harrison: Re: SDRAM quality
89297: 05/09/12: <stud_lang_jap@yahoo.com>: Fatal errror in ISE 6.3 i
89299: 05/09/12: Sean Durkin: Re: Fatal errror in ISE 6.3 i
89308: 05/09/12: Vladislav Muravin: Re: Fatal errror in ISE 6.3 i
89379: 05/09/13: <stud_lang_jap@yahoo.com>: Re: Fatal errror in ISE 6.3 i
89298: 05/09/12: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: place and route
89302: 05/09/12: Sven: Re: place and route
89314: 05/09/12: Phil Hays: Re: place and route
89365: 05/09/13: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: place and route
89373: 05/09/13: Austin Lesea: Re: place and route
89372: 05/09/13: Sven: Re: place and route
89388: 05/09/13: Sven: Re: place and route
89395: 05/09/14: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: place and route
89303: 05/09/12: walter zabel: xilinx ise / update schematics
89304: 05/09/12: adrian: Xilkernel problem
89310: 05/09/12: Nitesh: modelsim simulation problem
89313: 05/09/12: Sean Durkin: Re: modelsim simulation problem
89320: 05/09/12: Nitesh: Re: modelsim simulation problem
89317: 05/09/12: geoffrey wall: reducing the number of IOBS in a design
89319: 05/09/12: John_H: Re: reducing the number of IOBS in a design
89330: 05/09/13: Jim Wu: Re: reducing the number of IOBS in a design
89407: 05/09/14: Vladislav Muravin: Re: reducing the number of IOBS in a design
89318: 05/09/12: Ram: ISE 7.1i & Linux / reg code question
89322: 05/09/12: Adrian Knoth: Re: ISE 7.1i & Linux / reg code question
89325: 05/09/12: Duane Clark: Re: ISE 7.1i & Linux / reg code question
89328: 05/09/13: Jim Wu: Re: ISE 7.1i & Linux / reg code question
89348: 05/09/13: Ram: Re: ISE 7.1i & Linux / reg code question
89354: 05/09/13: B. Joshua Rosen: Re: ISE 7.1i & Linux / reg code question
89367: 05/09/13: Ram: Re: ISE 7.1i & Linux / reg code question
89533: 05/09/18: John McCluskey: Re: ISE 7.1i & Linux / reg code question
90473: 05/10/13: Eric Smith: Re: ISE 7.1i & Linux / reg code question
89364: 05/09/13: kmlpatel@gmail.com: Re: ISE 7.1i & Linux / reg code question
89321: 05/09/12: Ram: Microblaze & Memory DMA operation
89323: 05/09/12: Adrian Knoth: Re: Microblaze & Memory DMA operation
89337: 05/09/13: =?ISO-8859-1?Q?G=F6ran_Bilski?=: Re: Microblaze & Memory DMA operation
89349: 05/09/13: Ram: Re: Microblaze & Memory DMA operation
89357: 05/09/13: =?UTF-8?B?R8O2cmFuIEJpbHNraQ==?=: Re: Microblaze & Memory DMA operation
89370: 05/09/13: Ram: Re: Microblaze & Memory DMA operation
89390: 05/09/14: =?UTF-8?B?R8O2cmFuIEJpbHNraQ==?=: Re: Microblaze & Memory DMA operation
89418: 05/09/14: Terry Fowler: Re: Microblaze & Memory DMA operation
89436: 05/09/15: Zara: Re: Microblaze & Memory DMA operation
89515: 05/09/16: Terry Fowler: Re: Microblaze & Memory DMA operation
89442: 05/09/15: =?ISO-8859-1?Q?G=F6ran_Bilski?=: Re: Microblaze & Memory DMA operation
90993: 05/10/26: Terry Fowler: Re: Microblaze & Memory DMA operation
91036: 05/10/27: Terry Fowler: Re: Microblaze & Memory DMA operation
89327: 05/09/12: <junnuthula@yahoo.com>: Please Help:Modelsim-Altera License "Verilog Computer Based training course"
89329: 05/09/12: biot: FFT implementation in Xilinx's Spartan 3
89333: 05/09/13: Zara: Re: FFT implementation in Xilinx's Spartan 3
89346: 05/09/13: Jens Baumann: Re: FFT implementation in Xilinx's Spartan 3
89347: 05/09/13: biot: Re: FFT implementation in Xilinx's Spartan 3
89334: 05/09/13: Adrian: P&R speed higher than synthesis
89343: 05/09/13: JJ: Re: P&R speed higher than synthesis
89336: 05/09/13: Paul Gentieu: CPU benchmark for Xilinx PAR
89338: 05/09/13: John Adair: Re: CPU benchmark for Xilinx PAR
89342: 05/09/13: JJ: Re: CPU benchmark for Xilinx PAR
89351: 05/09/13: B. Joshua Rosen: Re: CPU benchmark for Xilinx PAR
89536: 05/09/18: concerned_altera: Re: CPU benchmark for Xilinx PAR
89403: 05/09/14: Vladislav Muravin: Re: CPU benchmark for Xilinx PAR
89404: 05/09/14: B. Joshua Rosen: Re: CPU benchmark for Xilinx PAR
89410: 05/09/14: John_H: Re: CPU benchmark for Xilinx PAR
89470: 05/09/15: Bret Wade: Re: CPU benchmark for Xilinx PAR
89408: 05/09/14: Brannon: Re: CPU benchmark for Xilinx PAR
89339: 05/09/13: <apsolar@gmail.com>: Tree Representation of Logic Circuits
89387: 05/09/14: Ulrich Bangert: Re: Tree Representation of Logic Circuits
89340: 05/09/13: Manfred Balik: Migration Altera APEX20KE to ???
89377: 05/09/13: Daniel Lang: Re: Migration Altera APEX20KE to ???
89389: 05/09/13: htoerrin: Re: Migration Altera APEX20KE to ???
89476: 05/09/15: Vaughn Betz: Re: Migration Altera APEX20KE to ???
89435: 05/09/14: HamishR: Re: Migration Altera APEX20KE to ???
89361: 05/09/13: Le.Wang: 24 Counters on one board
89362: 05/09/13: Phil Hays: Re: 24 Counters on one board
89368: 05/09/14: Jim Granville: Re: 24 Counters on one board
89392: 05/09/14: Simon Peacock: Re: 24 Counters on one board
89393: 05/09/14: Le.Wang: Re: 24 Counters on one board
89363: 05/09/13: Soenke: floppycontroller
89369: 05/09/13: Finn S. Nielsen: Spartan-3 1000 -5 availability
89394: 05/09/14: Simon Peacock: Re: Spartan-3 1000 -5 availability
89409: 05/09/14: Austin Lesea: Re: Spartan-3 1000 -5 availability
89371: 05/09/13: Remco: FIFO design using Virtex-II block ram..
89374: 05/09/13: John_H: Re: FIFO design using Virtex-II block ram..
89402: 05/09/14: Vladislav Muravin: Re: FIFO design using Virtex-II block ram..
89414: 05/09/14: Mike Treseler: Re: FIFO design using Virtex-II block ram..
89434: 05/09/15: jtw: Re: FIFO design using Virtex-II block ram..
89406: 05/09/14: Remco: Re: FIFO design using Virtex-II block ram..
89416: 05/09/14: Remco: Re: FIFO design using Virtex-II block ram..
89375: 05/09/13: bassos: edk service pack download
89376: 05/09/13: they call me frenchy: Is a CPLD appropriate for this triple PWM application?
89380: 05/09/14: Jim Granville: Re: Is a CPLD appropriate for this triple PWM application?
89412: 05/09/14: they call me frenchy: Re: Is a CPLD appropriate for this triple PWM application?
89423: 05/09/15: Jim Granville: Re: Is a CPLD appropriate for this triple PWM application?
89462: 05/09/15: they call me frenchy: Re: Is a CPLD appropriate for this triple PWM application?
89444: 05/09/15: David Brown: Re: Is a CPLD appropriate for this triple PWM application?
89458: 05/09/15: they call me frenchy: Re: Is a CPLD appropriate for this triple PWM application?
89469: 05/09/16: Jim Granville: Re: Is a CPLD appropriate for this triple PWM application?
89479: 05/09/16: David Brown: Re: Is a CPLD appropriate for this triple PWM application?
89500: 05/09/16: they call me frenchy: Re: Is a CPLD appropriate for this triple PWM application?
89550: 05/09/19: David Brown: Re: Is a CPLD appropriate for this triple PWM application?
89382: 05/09/14: Luis Cupido: Re: Is a CPLD appropriate for this triple PWM application?
89413: 05/09/14: they call me frenchy: Re: Is a CPLD appropriate for this triple PWM application?
89426: 05/09/15: Luis Cupido: Re: Is a CPLD appropriate for this triple PWM application?
89464: 05/09/15: they call me frenchy: Re: Is a CPLD appropriate for this triple PWM application?
89471: 05/09/15: Luis Cupido: Re: Is a CPLD appropriate for this triple PWM application?
89502: 05/09/16: they call me frenchy: Re: Is a CPLD appropriate for this triple PWM application?
89503: 05/09/16: Falk Brunner: Re: Is a CPLD appropriate for this triple PWM application?
89510: 05/09/16: they call me frenchy: Re: Is a CPLD appropriate for this triple PWM application?
89513: 05/09/16: Falk Brunner: Re: Is a CPLD appropriate for this triple PWM application?
89562: 05/09/19: they call me frenchy: Re: Is a CPLD appropriate for this triple PWM application?
89569: 05/09/20: Jim Granville: Re: Is a CPLD appropriate for this triple PWM application?
89415: 05/09/14: they call me frenchy: Re: Is a CPLD appropriate for this triple PWM application?
89421: 05/09/14: Gabor: Re: Is a CPLD appropriate for this triple PWM application?
89472: 05/09/15: <kevinjwhite@comcast.net>: Re: Is a CPLD appropriate for this triple PWM application?
89381: 05/09/13: seb_tech_fr: XilinX MAC FIR
89397: 05/09/14: Ben Jones: Re: XilinX MAC FIR
89535: 05/09/18: John McCluskey: Re: XilinX MAC FIR
89548: 05/09/19: seb_tech_fr: re:XilinX MAC FIR
89383: 05/09/13: vssumesh: fan out capability of FPGA
89385: 05/09/14: Mark McDougall: Re: fan out capability of FPGA
89386: 05/09/14: Mark McDougall: Re: fan out capability of FPGA
89398: 05/09/14: Kolja Sulimma: Re: fan out capability of FPGA
89401: 05/09/14: Vladislav Muravin: Re: fan out capability of FPGA
89501: 05/09/16: Ed McGettigan: Re: fan out capability of FPGA
89496: 05/09/16: vssumesh: Re: fan out capability of FPGA
89384: 05/09/13: <sudarangareddy@yahoo.com>: ARM IP Core implementation in FPGA
89399: 05/09/14: Joseph: Re: ARM IP Core implementation in FPGA
89391: 05/09/14: biot: FFT implementation in Xilinx Spartan 3 started kit
89396: 05/09/14: Aurelian Lazarut: Re: FFT implementation in Xilinx Spartan 3 started kit
89400: 05/09/14: Vladislav Muravin: Re: FFT implementation in Xilinx Spartan 3 started kit
89419: 05/09/14: Vladislav Muravin: Re: FFT implementation in Xilinx Spartan 3 started kit
89428: 05/09/14: Dave: Re: FFT implementation in Xilinx Spartan 3 started kit
89411: 05/09/14: biot: Re: FFT implementation in Xilinx Spartan 3 started kit
89437: 05/09/14: biot: Re: FFT implementation in Xilinx Spartan 3 started kit
89459: 05/09/15: Eric: Re: FFT implementation in Xilinx Spartan 3 started kit
89405: 05/09/14: DIGONNET Daniel: TAP controller
89417: 05/09/14: Eric: USB tranciever + controller in FPGA
89427: 05/09/14: johnp: Re: USB tranciever + controller in FPGA
89557: 05/09/19: John M: Re: USB tranciever + controller in FPGA
89420: 05/09/14: JTW: VHDL: Address Decoder
89422: 05/09/14: Mike Treseler: Re: VHDL: Address Decoder
89424: 05/09/14: Symon: Re: VHDL: Address Decoder
89431: 05/09/14: Weddick: Re: VHDL: Address Decoder
89432: 05/09/14: Weddick: Re: Address Decoder
89425: 05/09/14: <DerekSimmons@FrontierNet.net>: Looking for a DIgital Systems book with JPEG example code
89463: 05/09/15: Randy Yates: Re: Looking for a DIgital Systems book with JPEG example code
89477: 05/09/15: <onyx49@juno.com>: Re: Looking for a DIgital Systems book with JPEG example code
89429: 05/09/15: Paul Urbanus: IP Protection of code block in Xilinx FPGA?
89451: 05/09/15: Mike Treseler: Re: IP Protection of code block in Xilinx FPGA?
89456: 05/09/15: Paul Urbanus: Re: IP Protection of code block in Xilinx FPGA?
89480: 05/09/16: Martin Thompson: Re: IP Protection of code block in Xilinx FPGA?
89489: 05/09/16: Alvin Andries: Re: IP Protection of code block in Xilinx FPGA?
89430: 05/09/15: Mike Zhang: PCI configuration questions.
89433: 05/09/14: Joel Kolstad: Re: PCI configuration questions.
89439: 05/09/14: Mike: Re: PCI configuration questions.
89455: 05/09/15: Kevin Brace: Re: PCI configuration questions.
89466: 05/09/15: Mike: Re: PCI configuration questions.
89438: 05/09/14: <faaizal@gmail.com>: Matched Filter
89440: 05/09/14: logjam: HAL fuse map organization issue
89441: 05/09/14: logjam: Re: HAL fuse map organization issue
89445: 05/09/15: TTigger: Re: Address Decoder
89446: 05/09/15: Nemesis: ISE 7.1 service packs
89450: 05/09/15: Marco: Re: ISE 7.1 service packs
89448: 05/09/15: Mancini Stephane: Xilinx V2Pro & SATA hard disk
89452: 05/09/15: Alex Gibson: Re: Xilinx V2Pro & SATA hard disk
89454: 05/09/15: Mancini Stephane: Re: Xilinx V2Pro & SATA hard disk
89457: 05/09/15: Ed McGettigan: Re: Xilinx V2Pro & SATA hard disk
89449: 05/09/15: Robin Bruce: Starbridge Hypercomputer & Viva
89465: 05/09/15: c d saunter: Re: Starbridge Hypercomputer & Viva
89460: 05/09/15: Udo: Small (OEM-)Memory Modules (SRAM/FLASH/DRAM)
89461: 05/09/15: JJ: Re: Small (OEM-)Memory Modules (SRAM/FLASH/DRAM)
89478: 05/09/16: Kolja Sulimma: Re: Small (OEM-)Memory Modules (SRAM/FLASH/DRAM)
89589: 05/09/20: Udo: Re: Small (OEM-)Memory Modules (SRAM/FLASH/DRAM)
89473: 05/09/15: fahadislam2002: SDRAM HOW?
89481: 05/09/16: Mike Harrison: Re: SDRAM HOW?
89521: 05/09/17: dlharmon: Re: SDRAM HOW?
89482: 05/09/16: Mike Harrison: Re: SDRAM HOW?
89499: 05/09/16: Tony30: re:SDRAM HOW?
89474: 05/09/15: Brad Smallridge: Xilinx ML403
89505: 05/09/16: Ed McGettigan: Re: Xilinx ML403
89509: 05/09/16: Brad Smallridge: Re: Xilinx ML403
89516: 05/09/16: Ed McGettigan: Re: Xilinx ML403
89563: 05/09/19: Brad Smallridge: Re: Xilinx ML403
89565: 05/09/19: Ed McGettigan: Re: Xilinx ML403
89571: 05/09/19: Brad Smallridge: Re: Xilinx ML403
89558: 05/09/19: Martin Thompson: Re: Xilinx ML403
89560: 05/09/19: Brad Smallridge: Re: Xilinx ML403
89475: 05/09/15: lina: flash on P160 Module
89483: 05/09/16: Neill A: Version Control Software
89485: 05/09/16: Adam Megacz: Re: Version Control Software (darcs recommended)
89508: 05/09/16: Andy Peters: Re: Version Control Software
89819: 05/09/27: Paul: Re: Version Control Software
89855: 05/09/28: Paul: Re: Version Control Software
89867: 05/09/28: Duane Clark: Re: Version Control Software
89972: 05/09/30: Duane Clark: Re: Version Control Software
89838: 05/09/27: <assaf_sarfati@yahoo.com>: Re: Version Control Software
89858: 05/09/28: Brandon: Re: Version Control Software
89883: 05/09/29: David Brown: Re: Version Control Software
89911: 05/09/30: David Brown: Re: Version Control Software
89865: 05/09/28: Andy Peters: Re: Version Control Software
89866: 05/09/28: Paul Marciano: Re: Version Control Software
89886: 05/09/29: Brandon: Re: Version Control Software
89961: 05/09/30: Andy Peters: Re: Version Control Software
89963: 05/09/30: Andy Peters: Re: Version Control Software
89965: 05/09/30: <assaf_sarfati@yahoo.com>: Re: Version Control Software
89484: 05/09/16: Ashok: ISE 7.1 on Linux, ngdbuild failed without error
89486: 05/09/16: zoinks@mytrashmail.com: DCM question
89487: 05/09/16: Zara: Re: DCM question
89490: 05/09/16: Marc Randolph: Re: DCM question
89493: 05/09/16: John_H: Re: DCM question
89507: 05/09/16: Brad Smallridge: Re: DCM question
89488: 05/09/16: Sleep Mode: problem with programming avnet edk board over LPT
89492: 05/09/16: Zara: Re: problem with programming avnet edk board over LPT
89494: 05/09/16: Sleep Mode: Re: problem with programming avnet edk board over LPT
89495: 05/09/16: Zara: Re: problem with programming avnet edk board over LPT
89497: 05/09/16: Yannis Koryfidis: Re: problem with programming avnet edk board over LPT
89504: 05/09/16: Sean Durkin: Re: problem with programming avnet edk board over LPT
89512: 05/09/16: Yannis Koryfidis: Re: problem with programming avnet edk board over LPT
89498: 05/09/16: Yannis Koryfidis: Re: problem with programming avnet edk board over LPT
89491: 05/09/16: Marco: Interrupt Handling
89506: 05/09/16: <alessandro.strazzero@virgilio.it>: DEV_CLRn and CRC_ERROR on ALTERA Cyclone
89518: 05/09/17: Rob: Re: DEV_CLRn and CRC_ERROR on ALTERA Cyclone
89514: 05/09/16: radarman: Looking for info on the V8/Arclite MicroRISC 8-bit core
89517: 05/09/16: athena: how to set OPB EMC for flash use?
89570: 05/09/19: joe4702: Re: how to set OPB EMC for flash use?
89584: 05/09/20: Athena: Re: how to set OPB EMC for flash use?
89600: 05/09/20: Duane Clark: Re: how to set OPB EMC for flash use?
89601: 05/09/20: Duane Clark: Re: how to set OPB EMC for flash use?
89619: 05/09/20: Athena: Re: how to set OPB EMC for flash use?
89520: 05/09/16: CMOS: Digilent USB2 module in B1 expansion slot
89523: 05/09/17: Telenochek: Software tools for architectural diagrams and for timing diagram entry?
89524: 05/09/17: JJ: Re: Software tools for architectural diagrams and for timing diagram entry?
89525: 05/09/17: Mike Treseler: Re: Software tools for architectural diagrams and for timing diagram
89527: 05/09/17: Telenochek: Re: Software tools for architectural diagrams and for timing diagram entry?
89526: 05/09/17: Pete Fraser: Insight / Xilinx Spartan II Demo Board files?
89529: 05/09/18: Marco: Xilinx Wizard does not create vhdl DMA template?
89532: 05/09/18: mte01: Using BRAMs in VHDL on Virtex II FPGAs
89575: 05/09/19: Paul Lee: Re: Using BRAMs in VHDL on Virtex II FPGAs
89577: 05/09/19: Mike Treseler: Re: Using BRAMs in VHDL on Virtex II FPGAs
89537: 05/09/18: Le.Wang: Dll device for FPGA
89551: 05/09/19: Alex: Re: Dll device for FPGA
89541: 05/09/18: Steven J. Hill: [PATCH] Xilinx Linux driver package clean-up.
89542: 05/09/19: Garrick: Generating Modelsim Verilog resource libraries - pointers/questions
89544: 05/09/19: Kim Enkovaara: Re: Generating Modelsim Verilog resource libraries - pointers/questions
89573: 05/09/19: Garrick: Re: Generating Modelsim Verilog resource libraries - pointers/questions
89583: 05/09/20: Kim Enkovaara: Re: Generating Modelsim Verilog resource libraries - pointers/questions
89612: 05/09/20: Garrick: Re: Generating Modelsim Verilog resource libraries - pointers/questions
89614: 05/09/20: Garrick: Re: Generating Modelsim Verilog resource libraries - pointers/questions
89629: 05/09/21: Kim Enkovaara: Re: Generating Modelsim Verilog resource libraries - pointers/questions
89543: 05/09/18: Zara: Re: Microblaze & Memory DMA operation
89545: 05/09/19: Frank van Eijkelenburg: Using two PowerPCs
89546: 05/09/19: Frank: Modelsim XE, what's the latest version?
89547: 05/09/19: Frank: Re: Modelsim XE, what's the latest version?
89552: 05/09/19: Simon Peacock: Re: Modelsim XE, what's the latest version?
89581: 05/09/20: Frank: Re: Modelsim XE, what's the latest version?
89585: 05/09/20: Frank: Re: Modelsim XE, what's the latest version?
89623: 05/09/21: do_not_reply: Re: Modelsim XE, what's the latest version?
89671: 05/09/21: gliss: re:Modelsim XE, what's the latest version?
89549: 05/09/19: u_stadler@yahoo.de: modelsim
89553: 05/09/19: <pei@uwiep.com>: Testbench failures for Opencores Ethernet mac
89554: 05/09/19: Jock: Reverse Engineering Output Files
89579: 05/09/19: Steven J. Hill: Re: Reverse Engineering Output Files
89556: 05/09/19: jai.dhar@gmail.com: FPGA's in bulk and pricing
89559: 05/09/19: Davide Anguita: Two short-term research grants
89561: 05/09/19: Hahnsolo: Unknown price difference for xilinx fpga
89592: 05/09/20: pipjockey: Re: Unknown price difference for xilinx fpga
89594: 05/09/20: Hahnsolo: Re: Unknown price difference for xilinx fpga
89564: 05/09/19: <bkuschak@gmail.com>: ISE 7.1i incremental synthesis
89670: 05/09/21: Stephan: Re: ISE 7.1i incremental synthesis
89736: 05/09/23: bkuschak@gmail.com: Re: ISE 7.1i incremental synthesis
89566: 05/09/19: <john.orlando@gmail.com>: Reprogramming FPGA over PCI???
89576: 05/09/19: Adrian Knoth: Re: Reprogramming FPGA over PCI???
89580: 05/09/20: Mark McDougall: Re: Reprogramming FPGA over PCI???
89588: 05/09/20: Kolja Sulimma: Re: Reprogramming FPGA over PCI???
89590: 05/09/20: <nahum_barnea@yahoo.com>: Re: Reprogramming FPGA over PCI???
89596: 05/09/20: Nial Stewart: Re: Reprogramming FPGA over PCI???
89599: 05/09/20: Peter Wallace: Re: Reprogramming FPGA over PCI???
89689: 05/09/22: Austin Franklin: Re: Reprogramming FPGA over PCI???
89694: 05/09/22: <john.orlando@gmail.com>: Re: Reprogramming FPGA over PCI???
89699: 05/09/22: Petter Gustad: Re: Reprogramming FPGA over PCI???
89567: 05/09/19: jai.dhar@gmail.com: FPGA's in bulk and pricing
89644: 05/09/21: GMM50: Re: FPGA's in bulk and pricing
89686: 05/09/22: jai.dhar@gmail.com: Re: FPGA's in bulk and pricing
89568: 05/09/19: EDK Simulation: Simulation : EDK
90845: 05/10/22: grupy: Re: Simulation : EDK
89572: 05/09/19: laoshan.zb@gmail.com: xilinx ML310 board PCI DMA problem
89680: 05/09/22: VB: Re: xilinx ML310 board PCI DMA problem
89578: 05/09/19: Luke: Re: Modelsim XE, what's the latest version?
89582: 05/09/19: gallen: Re: Modelsim XE, what's the latest version?
89586: 05/09/20: <nahum_barnea@yahoo.com>: program prom by the fpga
89587: 05/09/20: pinkotronic: problem with Thold violation under quartus
89609: 05/09/20: Mike Treseler: Re: problem with Thold violation under quartus
89616: 05/09/20: Peter Alfke: Re: problem with Thold violation under quartus
89627: 05/09/21: Subroto Datta: Re: problem with Thold violation under quartus
89591: 05/09/20: Ram: ISE 7.1i & Linux / reg code question
89598: 05/09/20: Adrian Knoth: Re: ISE 7.1i & Linux / reg code question
89593: 05/09/20: kagior: SoC embedded FPGA
89595: 05/09/20: Zara: Re: SoC embedded FPGA
89602: 05/09/20: Joseph: Re: SoC embedded FPGA
89597: 05/09/20: Tom Twist: Re: SoC embedded FPGA
89673: 05/09/21: <ningxue2000@yahoo.com>: Re: SoC embedded FPGA
89603: 05/09/20: M6: picoblaze IDE for Linux
89630: 05/09/21: Stephane: Re: picoblaze IDE for Linux
89679: 05/09/22: <francesco_poderico@yahoo.com>: Re: picoblaze IDE for Linux
89700: 05/09/22: Adrian Knoth: Re: picoblaze IDE for Linux
89696: 05/09/22: M6: Re: picoblaze IDE for Linux
89706: 05/09/22: M6: Re: picoblaze IDE for Linux
89604: 05/09/20: Roger: Core import into ISE
89605: 05/09/20: Duane Clark: Re: Core import into ISE
89607: 05/09/20: Roger: Re: Core import into ISE
89610: 05/09/20: Duane Clark: Re: Core import into ISE
89615: 05/09/20: Roger: Re: Core import into ISE
89606: 05/09/20: Nitesh: OPB bus communication
89669: 05/09/21: melbadri: Re: OPB bus communication
89734: 05/09/23: Sylvain Munaut: Re: OPB bus communication
89723: 05/09/23: Nitesh: Re: OPB bus communication
89741: 05/09/23: Nitesh: Re: OPB bus communication
89608: 05/09/20: <sharp@cadence.com>: Re: Modelsim XE, what's the latest version?
89611: 05/09/20: Austin Franklin: XST equivelent for Synplify "synthesis syn_preserve = 1"
89617: 05/09/20: Austin Franklin: Re: XST equivelent for Synplify "synthesis syn_preserve = 1"
89642: 05/09/21: Austin Franklin: Re: XST equivelent for Synplify "synthesis syn_preserve = 1"
89613: 05/09/20: praetorian: EDK libgen cc choice
89618: 05/09/20: fecs2: JTAG USB Circuit
89622: 05/09/21: Al Clark: Re: JTAG USB Circuit
89624: 05/09/20: GPE: Re: JTAG USB Circuit
89638: 05/09/21: Sean Durkin: Re: JTAG USB Circuit
89672: 05/09/21: GPE: Re: JTAG USB Circuit
89654: 05/09/21: <janbeck@gmail.com>: Re: JTAG USB Circuit
89620: 05/09/20: Andrew FPGA: Xilinx ISE Passing IO pad attributes using UCF file.
89621: 05/09/21: Bob Perlman: Re: Xilinx ISE Passing IO pad attributes using UCF file.
89625: 05/09/20: Andrew FPGA: Re: Xilinx ISE Passing IO pad attributes using UCF file.
89626: 05/09/20: gallen: Re: Modelsim XE, what's the latest version?
89628: 05/09/20: CMOS: digilent USB2 module
89631: 05/09/21: Alex Freed: Re: digilent USB2 module
89648: 05/09/21: CMOS: Re: digilent USB2 module
89649: 05/09/21: CMOS: Re: digilent USB2 module
89632: 05/09/21: hetfield: Count "1" bit in bit stream
89634: 05/09/21: David Brown: Re: Count "1" bit in bit stream
89641: 05/09/21: John_H: Re: Count "1" bit in bit stream
89643: 05/09/21: Thomas Womack: Re: Count "1" bit in bit stream
89635: 05/09/21: hetfield: Re: Count "1" bit in bit stream
89637: 05/09/21: Gabor: Re: Count "1" bit in bit stream
89640: 05/09/21: hetfield: Re: Count "1" bit in bit stream
89658: 05/09/21: Peter Alfke: Re: Count "1" bit in bit stream
89675: 05/09/21: hetfield: Re: Count "1" bit in bit stream
89993: 05/10/01: Thomas Rudloff: Re: Count "1" bit in bit stream
89633: 05/09/21: <ALuPin@web.de>: Output register instantiation in Quartus
89639: 05/09/21: Subroto Datta: Re: Output register instantiation in Quartus
89674: 05/09/22: Subroto Datta: Re: Output register instantiation in Quartus
89705: 05/09/22: Vaughn Betz: Re: Output register instantiation in Quartus
89753: 05/09/24: Subroto Datta: Re: Output register instantiation in Quartus
89646: 05/09/21: <ALuPin@web.de>: Re: Output register instantiation in Quartus
89678: 05/09/22: <ALuPin@web.de>: Re: Output register instantiation in Quartus
89683: 05/09/22: <ALuPin@web.de>: Re: Output register instantiation in Quartus
89708: 05/09/23: <ALuPin@web.de>: Re: Output register instantiation in Quartus
89636: 05/09/21: Aj: Re: XST equivelent for Synplify "synthesis syn_preserve = 1"
89645: 05/09/21: GMM50: Cyclone and NIOS II
89647: 05/09/21: Brad Smallridge: Xilinx ModelSim VHDL Running Two Models
89656: 05/09/21: Andy Peters: Re: Xilinx ModelSim VHDL Running Two Models
89666: 05/09/21: Brad Smallridge: Re: Xilinx ModelSim VHDL Running Two Models
89692: 05/09/22: Brad Smallridge: Re: Xilinx ModelSim VHDL Running Two Models
89748: 05/09/23: Brad Smallridge: Re: Xilinx ModelSim VHDL Running Two Models
89693: 05/09/22: Brad Smallridge: Re: Xilinx ModelSim VHDL Running Two Models
89676: 05/09/21: Nicolas Matringe: Re: Xilinx ModelSim VHDL Running Two Models
89677: 05/09/21: Nicolas Matringe: Re: Xilinx ModelSim VHDL Running Two Models
89730: 05/09/23: Andy Peters: Re: Xilinx ModelSim VHDL Running Two Models
89650: 05/09/21: acetylcholinerd@gmail.com: Xilinx Spartan-3
89651: 05/09/21: Austin Lesea: Re: Xilinx Spartan-3
89660: 05/09/21: Austin Lesea: Re: Xilinx Spartan-3
89667: 05/09/21: Austin Lesea: Re: Xilinx Spartan-3
89772: 05/09/26: Alvin Andries: Re: Xilinx Spartan-3
89652: 05/09/21: acetylcholinerd@gmail.com: Re: Xilinx Spartan-3
89659: 05/09/21: Peter Alfke: Re: Xilinx Spartan-3
89665: 05/09/21: acetylcholinerd@gmail.com: Re: Xilinx Spartan-3
89682: 05/09/22: sulimma: Re: Xilinx Spartan-3
89687: 05/09/22: acetylcholinerd@gmail.com: Re: Xilinx Spartan-3
89704: 05/09/22: Brian Davis: Re: Xilinx Spartan-3
89775: 05/09/26: Brian Davis: Re: Xilinx Spartan-3
89653: 05/09/21: <janbeck@gmail.com>: data logging via JTAG?
89655: 05/09/21: Ed McGettigan: Re: data logging via JTAG?
89709: 05/09/23: Hans: Re: data logging via JTAG?
89657: 05/09/21: Ajeetha: Re: Modelsim XE, what's the latest version?
89661: 05/09/21: stbcasa: Xilinx Webpack Schematic
89663: 05/09/21: Jon Elson: Re: Xilinx Webpack Schematic
89685: 05/09/22: Gabor: Re: Xilinx Webpack Schematic
89662: 05/09/21: sarnaths@gmail.com: JBits query
89688: 05/09/22: Stephen Craven: Re: JBits query
89664: 05/09/21: CloneNumber66: Altera Programming Cables and EPCS16/64
89668: 05/09/21: melbadri: opb ip master/slave...arbiter problems
89732: 05/09/23: Mohammed Elbadri: Re: opb ip master/slave...arbiter problems
89681: 05/09/22: VB: USB communication using PCI Logicore
89684: 05/09/22: nospam.eric@gmail.com: Network-on-Chip Architectures
89690: 05/09/22: Julian Kain: Xilinx PAR -- WARNING:Route - CLK Net may have excessive skew...
89777: 05/09/26: Gabor: Re: Xilinx PAR -- WARNING:Route - CLK Net may have excessive skew...
89691: 05/09/22: Giox: Hints for efficient 32 bit multiplier
89695: 05/09/22: mk: Re: Hints for efficient 32 bit multiplier
89702: 05/09/22: Sylvain Munaut: Re: Hints for efficient 32 bit multiplier
89703: 05/09/22: Ray Andraka: Re: Hints for efficient 32 bit multiplier
89712: 05/09/23: Giox: Re: Hints for efficient 32 bit multiplier
89697: 05/09/22: Anuja: downlaoding bit files to Xilinx FPGA
89698: 05/09/22: Falk Brunner: Re: downlaoding bit files to Xilinx FPGA
89721: 05/09/23: Falk Brunner: Re: downlaoding bit files to Xilinx FPGA
89701: 05/09/22: Stephen Craven: Re: downlaoding bit files to Xilinx FPGA
89744: 05/09/24: Philip Freidin: Re: downlaoding bit files to Xilinx FPGA
89713: 05/09/23: Anuja: Re: downlaoding bit files to Xilinx FPGA
89715: 05/09/23: Anuja: Re: downlaoding bit files to Xilinx FPGA
89718: 05/09/23: johnp: Re: downlaoding bit files to Xilinx FPGA
89719: 05/09/23: johnp: Re: downlaoding bit files to Xilinx FPGA
89738: 05/09/23: Anuja: Re: downlaoding bit files to Xilinx FPGA
89782: 05/09/26: Anuja: Re: downlaoding bit files to Xilinx FPGA
89795: 05/09/26: Stephen Craven: Re: downlaoding bit files to Xilinx FPGA
89869: 05/09/28: Anuja: Re: downlaoding bit files to Xilinx FPGA
89707: 05/09/23: Mark Christiaens: Announcement Free Symposium on the Future of Configurable Hardware
89710: 05/09/23: <jerryjsy@hotmail.com>: Need help in Flash simulation module.
89711: 05/09/23: Simon Heinzle: Synchronizer Flip Flop / Metastability
89714: 05/09/23: B. Joshua Rosen: Re: Synchronizer Flip Flop / Metastability
89716: 05/09/23: Gabor: Re: Synchronizer Flip Flop / Metastability
89717: 05/09/23: Phil Hays: Re: Synchronizer Flip Flop / Metastability
89728: 05/09/23: Symon: Re: Synchronizer Flip Flop / Metastability
89823: 05/09/27: Symon: Re: Synchronizer Flip Flop / Metastability
89824: 05/09/27: B. Joshua Rosen: Re: Synchronizer Flip Flop / Metastability
89825: 05/09/27: Symon: Re: Synchronizer Flip Flop / Metastability
90362: 05/10/11: Hal Murray: Re: Synchronizer Flip Flop / Metastability
89729: 05/09/23: Peter Alfke: Re: Synchronizer Flip Flop / Metastability
89766: 05/09/26: Simon Heinzle: Re: Synchronizer Flip Flop / Metastability
89798: 05/09/26: rhnlogic@yahoo.com: Re: Synchronizer Flip Flop / Metastability
89806: 05/09/26: Peter Alfke: Re: Synchronizer Flip Flop / Metastability
89829: 05/09/27: rhnlogic@yahoo.com: Re: Synchronizer Flip Flop / Metastability
89834: 05/09/27: Peter Alfke: Re: Synchronizer Flip Flop / Metastability
89720: 05/09/23: Stephen Craven: C-to-gates experiences
89724: 05/09/23: Robin Bruce: Re: C-to-gates experiences
89726: 05/09/23: JJ: Re: C-to-gates experiences
89778: 05/09/26: fortiz80@gmail.com: Re: C-to-gates experiences
89722: 05/09/23: shorty: Power Management for Xilinx and Altera FPGAs
89737: 05/09/23: Teo: Re: Power Management for Xilinx and Altera FPGAs
89725: 05/09/23: S.T.: Linux USB XUP board
89727: 05/09/23: Adrian Knoth: Re: Linux USB XUP board
89771: 05/09/26: S.T.: Re: Linux USB XUP board
89731: 05/09/23: Antonio Pasini: ML403 dcm phase shift reference design... anyone has a copy ?
89733: 05/09/23: raul: Re: Modelsim XE, what's the latest version?
89735: 05/09/23: raul: Re: Modelsim XE, what's the latest version?
89739: 05/09/23: Alexey Kulentsov: 802.11g solution usable for FPGA design
89740: 05/09/23: MikeD': I need an Altera Excalib EPXA10 DDR Dev Board...anybody got one?
89742: 05/09/23: <francisontheweb@yahoo.com>: 10G serial port with no FEC?
89743: 05/09/23: Marc Randolph: Re: 10G serial port with no FEC?
89745: 05/09/23: GPE: Question on Metastability
89746: 05/09/23: Peter Alfke: Re: Question on Metastability
89756: 05/09/24: GPE: Re: Question on Metastability
89757: 05/09/25: Jim Granville: Re: Question on Metastability
89797: 05/09/26: GPE: Re: Question on Metastability
89750: 05/09/24: Stephan Flock: Re: Question on Metastability
89755: 05/09/24: GPE: Re: Question on Metastability
89791: 05/09/27: Jim Granville: Re: Question on Metastability
89796: 05/09/27: Jim Granville: Re: Question on Metastability
89752: 05/09/24: Peter Alfke: Re: Question on Metastability
89776: 05/09/26: Gabor: Re: Question on Metastability
89794: 05/09/26: Peter Alfke: Re: Question on Metastability
89747: 05/09/23: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: jbits
89765: 05/09/25: Adam Megacz: Re: jbits
89780: 05/09/26: Austin Lesea: Re: jbits & reverse engineering
89790: 05/09/26: Austin Lesea: Re: jbits & reverse engineering
89812: 05/09/27: Simon Peacock: Re: jbits & reverse engineering
89784: 05/09/26: Adam Megacz: Re: jbits & reverse engineering
89839: 05/09/27: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: jbits
89840: 05/09/27: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: jbits
89749: 05/09/24: Marco: "Free" core and license
89773: 05/09/26: Guenter: Re: "Free" core and license
89774: 05/09/26: Marco: Re: "Free" core and license
89799: 05/09/27: Rudolf Usselmann: Re: "Free" core and license
89751: 05/09/24: Pinhas: Re: Modelsim XE, what's the latest version?
89754: 05/09/24: Richard B. Katz: MAPLD 2005 Postings On-line
89801: 05/09/26: Bill McCulley: Re: MAPLD 2005 Postings On-line
89759: 05/09/25: Kutaj Vamor: Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments
89761: 05/09/25: Anton Erasmus: Re: Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments
89763: 05/09/25: Kevin Brace: Re: Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments
89955: 05/09/30: <troy.scott@latticesemi.com>: Re: Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments
90020: 05/10/02: PNowe: Re: Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments
157045: 14/09/13: pini_kr: Re: Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments
89760: 05/09/25: Piotr Wyderski: Cyclone on a shared configuration bus
89762: 05/09/25: <shihhsin.hu@gmail.com>: question about creating RPM
89805: 05/09/26: Jason Hu: Re: question about creating RPM
89764: 05/09/25: <pinod01@sympatico.ca>: Altera_VHDL_support library into Modelsim?
89786: 05/09/26: <pinod01@sympatico.ca>: Re: Altera_VHDL_support library into Modelsim?
89793: 05/09/26: <pinod01@sympatico.ca>: Re: Altera_VHDL_support library into Modelsim?
89767: 05/09/26: <ALuPin@web.de>: Making timing assignment in Quartus
89768: 05/09/26: <zoharl3@gmail.com>: altera new bee
89817: 05/09/27: jai.dhar@gmail.com: Re: altera new bee
90012: 05/10/01: <altera_smells@hotmail.com>: Re: altera new bee
90025: 05/10/03: Philip Freidin: Re: altera new bee
90028: 05/10/03: Simon Peacock: Re: altera new bee
89769: 05/09/26: K d: lwip sockets on spartan 3 microblaze? Any examples?
89808: 05/09/27: <francesco_poderico@yahoo.com>: Re: lwip sockets on spartan 3 microblaze? Any examples?
89813: 05/09/27: <john.orlando@gmail.com>: Re: lwip sockets on spartan 3 microblaze? Any examples?
89770: 05/09/26: codejk: External dpram similar to blockram of Xilinx device
89789: 05/09/26: Mike Treseler: Re: External dpram similar to blockram of Xilinx device
89779: 05/09/26: <VAX9000@gmail.com>: ALTERA quartus II 5.0sp1 web edition can't program MAXII: error code 84
89821: 05/09/27: Subroto Datta: Re: ALTERA quartus II 5.0sp1 web edition can't program MAXII: error code 84
89837: 05/09/27: <VAX9000@gmail.com>: Re: ALTERA quartus II 5.0sp1 web edition can't program MAXII: error code 84
89781: 05/09/26: S.T.: Xilinx XUP + Linux (firmware loading problem!)
89783: 05/09/26: CMOS: vhdl state maching problem
89785: 05/09/26: <pinod01@sympatico.ca>: Re: vhdl state maching problem
89788: 05/09/26: Brad Smallridge: Re: vhdl state maching problem
89807: 05/09/26: Nicolas Matringe: Re: vhdl state maching problem
89811: 05/09/27: Simon Peacock: RE: vhdl state maching problem
89815: 05/09/27: CMOS: Re: vhdl state maching problem
89941: 05/09/30: abeaujean@gillam-fei.be: Re: vhdl state maching problem
89787: 05/09/26: <assaf_sarfati@yahoo.com>: Spartan3E - problem in creating LVDS DDR pads
89802: 05/09/26: austin: Re: Spartan3E - problem in creating LVDS DDR pads
89810: 05/09/27: Simon Peacock: Re: Spartan3E - problem in creating LVDS DDR pads
89816: 05/09/27: <assaf_sarfati@yahoo.com>: Re: Spartan3E - problem in creating LVDS DDR pads
89792: 05/09/26: Nitesh: chipscope pro
89809: 05/09/27: Pasacco: Re: chipscope pro
89859: 05/09/28: Ed McGettigan: Re: chipscope pro
89828: 05/09/27: Nitesh: Re: chipscope pro
89830: 05/09/27: seb_tech_fr: re:chipscope pro
89833: 05/09/27: Nitesh: Re: chipscope pro
89861: 05/09/28: melbadri: Re: chipscope pro
89862: 05/09/28: Andy Peters: Re: chipscope pro
89864: 05/09/28: Nitesh: Re: chipscope pro
89879: 05/09/28: Nitesh: Re: chipscope pro
89800: 05/09/26: Jason Hu: How to run ngcbuild in windows xp environment?
89803: 05/09/26: Jason Hu: Re: How to run ngcbuild in windows xp environment?
89814: 05/09/27: Marco: Re: How to run ngcbuild in windows xp environment?
89804: 05/09/26: MikeD': Any suggestions for prototyping in an ARM environment?
89832: 05/09/27: Kris Vorwerk: Re: Any suggestions for prototyping in an ARM environment?
90474: 05/10/13: MikeD': Re: Any suggestions for prototyping in an ARM environment?
89818: 05/09/27: <seabrench@163.com>: Image Processing Algorithm based on FPGA?
89848: 05/09/28: Martin Thompson: Re: Image Processing Algorithm based on FPGA?
89820: 05/09/27: mice: Spartan-3 starter kit and digilent jtag-usb cable
89831: 05/09/27: mice: re:Spartan-3 starter kit and digilent jtag-usb cable
89822: 05/09/27: Waage: Sythesis software for Virtex-4
89826: 05/09/27: Newman: Re: Sythesis software for Virtex-4
89836: 05/09/27: Phil Hays: Re: Sythesis software for Virtex-4
89846: 05/09/28: Simon Peacock: Re: Sythesis software for Virtex-4
89873: 05/09/28: John_H: Re: Sythesis software for Virtex-4
89849: 05/09/28: Martin Thompson: Re: Sythesis software for Virtex-4
89844: 05/09/28: Eric DELAGE: Re: Sythesis software for Virtex-4
89850: 05/09/28: Ashok: Re: Sythesis software for Virtex-4
89857: 05/09/28: Waage: Re: Sythesis software for Virtex-4
89827: 05/09/27: Waage: I am planning to purchase a Virtex-4 Eval board.
89915: 05/09/30: Antti Lukats: Re: I am planning to purchase a Virtex-4 Eval board.
89970: 05/09/30: JASH: Re: I am planning to purchase a Virtex-4 Eval board.
89835: 05/09/27: PeterC: Dolby Digital AC-3 Decode on an FPGA - Possible ? Big ?
89842: 05/09/28: Kolja Sulimma: Re: Dolby Digital AC-3 Decode on an FPGA - Possible ? Big ?
89863: 05/09/28: <aholtzma@gmail.com>: Re: Dolby Digital AC-3 Decode on an FPGA - Possible ? Big ?
89841: 05/09/28: springzzz@gmail.com: a ISE installation problem on linux
89870: 05/09/28: Ram: Re: a ISE installation problem on linux
89887: 05/09/29: springzzz@gmail.com: Re: a ISE installation problem on linux
89843: 05/09/28: <francesco_poderico@yahoo.com>: Small C Compiler for Picoblaze
89845: 05/09/28: Jim Granville: Re: Small C Compiler for Picoblaze
89860: 05/09/28: Brad Smallridge: Re: Small C Compiler for Picoblaze
89888: 05/09/29: <francesco_poderico@yahoo.com>: Re: Small C Compiler for Picoblaze
89847: 05/09/28: Frank van Eijkelenburg: IPIF interface not fast enough
89852: 05/09/28: Sean Durkin: Re: IPIF interface not fast enough
89853: 05/09/28: Frank van Eijkelenburg: Re: IPIF interface not fast enough
89900: 05/09/29: Joseph Samson: Re: IPIF interface not fast enough
89851: 05/09/28: Designfreek: Internal clock for apex20ke
89854: 05/09/28: <amyler@eircom.net>: 16-bit microprocessor dore for Actel
89895: 05/09/29: Hans: Re: 16-bit microprocessor dore for Actel
89914: 05/09/30: Antti Lukats: Re: 16-bit microprocessor dore for Actel
89920: 05/09/30: Hans: Re: 16-bit microprocessor dore for Actel
89922: 05/09/30: Antti Lukats: Re: 16-bit microprocessor dore for Actel
90307: 05/10/10: Jonathan Bromley: Re: 16-bit microprocessor dore for Actel
90309: 05/10/10: Antti Lukats: Re: 16-bit microprocessor dore for Actel
90316: 05/10/10: Jonathan Bromley: Re: 16-bit microprocessor dore for Actel
90317: 05/10/10: Antti Lukats: Re: 16-bit microprocessor dore for Actel
90311: 05/10/10: Jim Granville: Re: 16-bit microprocessor dore for Actel
89856: 05/09/28: bijoy: FPGA : Decimation Filter
89898: 05/09/29: seb_tech_fr: re:FPGA : Decimation Filter
89926: 05/09/30: bijoy: Re: FPGA : Decimation Filter
90046: 05/10/03: seb_tech_fr: re:FPGA : Decimation Filter
89868: 05/09/28: Waage: Using 3rd Party FPGA flows and Xilinx
89877: 05/09/28: Newman: Re: Using 3rd Party FPGA flows and Xilinx
89871: 05/09/28: Ram: Pricing for V2-Pro / V4-FX ?
89872: 05/09/28: Ram: Req to Xilinx: eCos port for Microblaze
89878: 05/09/28: Peter Ryser: Re: Req to Xilinx: eCos port for Microblaze
90004: 05/10/01: Ram: Re: Req to Xilinx: eCos port for Microblaze
89874: 05/09/28: prasad babu: help needed
89876: 05/09/28: Kyle: newbie questions: Xilinx vs. Altera tools and parts
89881: 05/09/28: Phil Hays: Re: newbie questions: Xilinx vs. Altera tools and parts
89880: 05/09/29: Marco: Turion 64 performance
89882: 05/09/29: G.H. Hardy: Using LogicCORE on development board with Web ISE
89931: 05/09/30: Antti Lukats: Re: Using LogicCORE on development board with Web ISE
90017: 05/10/02: Kevin Brace: Re: Using LogicCORE on development board with Web ISE
90142: 05/10/05: Kevin Brace: Re: Using LogicCORE on development board with Web ISE
90064: 05/10/04: G.H. Hardy: Re: Using LogicCORE on development board with Web ISE
89884: 05/09/29: nospam.eric@gmail.com: ... failed to route using a CLK template
89919: 05/09/30: Martin Thompson: Re: ... failed to route using a CLK template
89885: 05/09/29: Andrew Greensted: Synchronous & Asymchrnous Flip Flop Implementation
89896: 05/09/29: sulimma: Re: Synchronous & Asymchrnous Flip Flop Implementation
89940: 05/09/30: Andrew Greensted: Re: Synchronous & Asymchrnous Flip Flop Implementation
89899: 05/09/29: Mike Treseler: Re: Synchronous & Asymchrnous Flip Flop Implementation
89889: 05/09/29: <pinod01@sympatico.ca>: Altera SOPC testbenching in Modelsim?
89890: 05/09/29: abhi: CPLD program editing
89897: 05/09/29: Rene Tschaggelar: Re: CPLD program editing
89913: 05/09/30: Antti Lukats: Re: CPLD program editing
89891: 05/09/29: Subhasri krishnan: Preloading SDRAM?
89892: 05/09/29: Gabor: Re: Preloading SDRAM?
89923: 05/09/30: Mike Harrison: Re: Preloading SDRAM?
89893: 05/09/29: Subhasri krishnan: Re: Preloading SDRAM?
89894: 05/09/29: Stephen Craven: Re: Preloading SDRAM?
89906: 05/09/30: backhus: Re: Preloading SDRAM?
89927: 05/09/30: Antti Lukats: Re: Preloading SDRAM?
89947: 05/09/30: Adrian Knoth: Re: Preloading SDRAM?
89901: 05/09/29: ivan: There is a way to instantiate 'N' VHDL components using a repetitive strutucture ?
89902: 05/09/30: Mark McDougall: Re: There is a way to instantiate 'N' VHDL components using a repetitive
89905: 05/09/30: backhus: Re: There is a way to instantiate 'N' VHDL components using a repetitive
89924: 05/09/30: Simon Peacock: Re: There is a way to instantiate 'N' VHDL components using a repetitive strutucture ?
89903: 05/09/29: wanch: High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if CLKIN > 140MHz
89904: 05/09/30: Zara: Re: High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if
89909: 05/09/30: Antti Lukats: Re: High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if CLKIN > 140MHz
90036: 05/10/03: Antti Lukats: Re: High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if CLKIN > 140MHz
89995: 05/10/01: wanch: Re: High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if CLKIN > 140MHz
89996: 05/10/01: wanch: Re: High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if CLKIN > 140MHz
90008: 05/10/01: Brian Davis: Re: High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if CLKIN > 140MHz
89907: 05/09/29: peri: very urgent
89908: 05/09/30: Antti Lukats: Antti is back
89917: 05/09/30: Jim Granville: Re: Antti is back
89921: 05/09/30: Thomas Entner: Re: Antti is back
89910: 05/09/30: Antti Lukats: Re: very urgent
90039: 05/10/03: Sandro: Re: Antti is back
89912: 05/09/30: Antti Lukats: best SPI flash configuration solution for Xilinx FPGA's
89916: 05/09/30: <francesco_poderico@yahoo.com>: Re: best SPI flash configuration solution for Xilinx FPGA's
89918: 05/09/30: Antti Lukats: Altera why so QUIET !?
90019: 05/10/03: Ben Twijnstra: Re: Altera why so QUIET !?
90053: 05/10/03: austin: Re: Altera why so QUIET !?
90086: 05/10/04: Ben Twijnstra: Re: Altera why so QUIET !?
90093: 05/10/04: Austin Lesea: EasyPath, demystified
90099: 05/10/04: Ben Twijnstra: Re: EasyPath, demystified
90103: 05/10/04: Austin Lesea: Re: EasyPath, demystified
90111: 05/10/04: Ray Andraka: Re: EasyPath, demystified
90119: 05/10/05: Ben Twijnstra: Re: EasyPath, demystified
90129: 05/10/05: Ben Jones: Re: EasyPath, demystified
90139: 05/10/05: Ben Twijnstra: Re: EasyPath, demystified
90145: 05/10/05: Austin Lesea: Re: EasyPath, demystified
90209: 05/10/06: Ben Twijnstra: Re: EasyPath, demystified
90102: 05/10/04: Austin Lesea: Re: EasyPath, demystified
90098: 05/10/04: Adam Megacz: Re: EasyPath, demystified
90108: 05/10/04: Adam Megacz: Re: EasyPath, demystified
90105: 05/10/04: johnp: Re: EasyPath, demystified
89925: 05/09/30: Antti Lukats: Help! I lost my life (Again)!
89928: 05/09/30: vssumesh: Prob in Synthesizing and Simulating large Mux
89930: 05/09/30: Antti Lukats: Re: Prob in Synthesizing and Simulating large Mux
89934: 05/09/30: Antti Lukats: Re: Prob in Synthesizing and Simulating large Mux
89944: 05/09/30: Kolja Sulimma: Re: Prob in Synthesizing and Simulating large Mux
90009: 05/10/01: Ray Andraka: Re: Prob in Synthesizing and Simulating large Mux
90029: 05/10/03: Simon Peacock: Re: Prob in Synthesizing and Simulating large Mux
90038: 05/10/03: Simon Peacock: Re: Prob in Synthesizing and Simulating large Mux
90058: 05/10/04: Simon Peacock: Re: Prob in Synthesizing and Simulating large Mux
90125: 05/10/05: Simon Peacock: Re: Prob in Synthesizing and Simulating large Mux
90169: 05/10/06: Simon Peacock: Re: Prob in Synthesizing and Simulating large Mux
89933: 05/09/30: vssumesh: Re: Prob in Synthesizing and Simulating large Mux
90024: 05/10/02: vssumesh: Re: Prob in Synthesizing and Simulating large Mux
90032: 05/10/03: vssumesh: Re: Prob in Synthesizing and Simulating large Mux
90040: 05/10/03: vssumesh: Re: Prob in Synthesizing and Simulating large Mux
90062: 05/10/04: vssumesh: Re: Prob in Synthesizing and Simulating large Mux
90077: 05/10/04: Andy Peters: Re: Prob in Synthesizing and Simulating large Mux
90136: 05/10/05: vssumesh: Re: Prob in Synthesizing and Simulating large Mux
89929: 05/09/30: Antti Lukats: looking for 1 beta-tester for PLD2HDL (XPLA3 edition) tool
89932: 05/09/30: Antti Lukats: Spartan II, Platfrom Flash, ISE 7.1 - SERIOUS PROBLEM
89935: 05/09/30: <praveen.kantharajapura@gmail.com>: Power on reset generation in FPGA
89936: 05/09/30: Antti Lukats: Re: Power on reset generation in FPGA
89954: 05/09/30: Duane Clark: Re: Power on reset generation in FPGA
90304: 05/10/10: Nial Stewart: Re: Power on reset generation in FPGA
90323: 05/10/10: Austin Lesea: Re: Power on reset generation in FPGA
90395: 05/10/11: Ray Andraka: Re: Power on reset generation in FPGA
90332: 05/10/10: Andrew FPGA: Re: Power on reset generation in FPGA
89937: 05/09/30: <fastgreen2000@yahoo.com>: Testbench using Modelsim/VHDL - simple signal generation problem
89938: 05/09/30: Zara: Re: Testbench using Modelsim/VHDL - simple signal generation problem
89946: 05/09/30: Zara: Re: Testbench using Modelsim/VHDL - simple signal generation problem
89988: 05/10/01: Simon Peacock: Re: Testbench using Modelsim/VHDL - simple signal generation problem
89939: 05/09/30: Mike Treseler: Re: Testbench using Modelsim/VHDL - simple signal generation problem
89942: 05/09/30: <fastgreen2000@yahoo.com>: Re: Testbench using Modelsim/VHDL - simple signal generation problem
89943: 05/09/30: <fastgreen2000@yahoo.com>: Re: Testbench using Modelsim/VHDL - simple signal generation problem
89948: 05/09/30: Newman: Re: Testbench using Modelsim/VHDL - simple signal generation problem
89956: 05/09/30: Duane Clark: Re: Testbench using Modelsim/VHDL - simple signal generation problem
89966: 05/09/30: Duane Clark: Re: Testbench using Modelsim/VHDL - simple signal generation problem
89960: 05/09/30: <fastgreen2000@yahoo.com>: Re: Testbench using Modelsim/VHDL - simple signal generation problem
89981: 05/09/30: perica: re:Testbench using Modelsim/VHDL - simple signal generation pro
89945: 05/09/30: John Adair: Prevue - FPGA Dev Board Sale
89971: 05/09/30: JASH: Re: Prevue - FPGA Dev Board Sale
89984: 05/10/01: John Adair: Re: Prevue - FPGA Dev Board Sale
89985: 05/10/01: =?ISO-8859-15?Q?Heinz=2DJ=FCrgen?= Oertel: Re: Prevue - FPGA Dev Board Sale
89994: 05/10/01: John Adair: Re: Prevue - FPGA Dev Board Sale
90018: 05/10/02: Kevin Brace: Re: Prevue - FPGA Dev Board Sale
89949: 05/09/30: Maki: Lattice XP availability
89950: 05/09/30: Antti Lukats: Re: Lattice XP availability
89952: 05/09/30: Antti Lukats: Re: Lattice XP availability
89951: 05/09/30: Maki: Re: Lattice XP availability
89953: 05/09/30: Antti Lukats: I, Wish: I had an Spartan-3e NOW!
90005: 05/10/01: <seannstifler69@hotmail.com>: Re: I, Wish: I had an Spartan-3e NOW!
90010: 05/10/01: Newman: Re: I, Wish: I had an Spartan-3e NOW!
90011: 05/10/01: Peter Alfke: Re: I, Wish: I had an Spartan-3e NOW!
89957: 05/09/30: <henrique.portela@gmail.com>: PCB Software....
89964: 05/09/30: Rene Tschaggelar: Re: PCB Software....
89967: 05/09/30: Falk Brunner: Re: PCB Software....
89969: 05/09/30: Falk Brunner: Re: PCB Software....
89968: 05/09/30: <henrique.portela@gmail.com>: Re: PCB Software....
89976: 05/09/30: <henrique.portela@gmail.com>: Re: PCB Software....
89983: 05/09/30: icegray: Re: PCB Software....
89987: 05/10/01: Simon Peacock: Re: PCB Software....
89959: 05/09/30: Pete Fraser: Xilinx dev board with high quality video?
89991: 05/10/01: Antti Lukats: Re: Xilinx dev board with high quality video?
89997: 05/10/01: Pete Fraser: Re: Xilinx dev board with high quality video?
89998: 05/10/01: Pete Fraser: Re: Xilinx dev board with high quality video?
90057: 05/10/04: Antti Lukats: Re: Xilinx dev board with high quality video?
90007: 05/10/02: Simon Peacock: Re: Xilinx dev board with high quality video?
90031: 05/10/03: Antti Lukats: Re: Xilinx dev board with high quality video?
90035: 05/10/03: Simon Peacock: Re: Xilinx dev board with high quality video?
90000: 05/10/01: Brad Smallridge: Re: Xilinx dev board with high quality video?
90002: 05/10/01: Pete Fraser: Re: Xilinx dev board with high quality video?
90003: 05/10/02: Thomas Entner: Re: Xilinx dev board with high quality video?
90047: 05/10/03: Ed McGettigan: Re: Xilinx dev board with high quality video?
90056: 05/10/04: Antti Lukats: Re: Xilinx dev board with high quality video?
90073: 05/10/04: Ed McGettigan: Re: Xilinx dev board with high quality video?
90075: 05/10/04: Antti Lukats: Re: Xilinx dev board with high quality video?
90131: 05/10/05: Simon Peacock: Re: Xilinx dev board with high quality video?
90071: 05/10/04: Ed McGettigan: Re: Xilinx dev board with high quality video?
90138: 05/10/05: Pete Fraser: Re: Xilinx dev board with high quality video?
90087: 05/10/04: Antonio Pasini: Re: Xilinx dev board with high quality video?
90054: 05/10/03: Jecel: Re: Xilinx dev board with high quality video?
90110: 05/10/04: Jecel: Re: Xilinx dev board with high quality video?
90112: 05/10/04: Jecel: Re: Xilinx dev board with high quality video?
89962: 05/09/30: Matthew Plante: Xilinx ISE 7.1i Portability Error
90033: 05/10/03: Adarsh Kumar Jain: Re: Xilinx ISE 7.1i Portability Error
90143: 05/10/05: Matthew Plante: Re: Xilinx ISE 7.1i Portability Error
89973: 05/09/30: geoffrey wall: fixed point dot product with log2(n) pipe stages in vhdl
90308: 05/10/10: Jonathan Bromley: Re: fixed point dot product with log2(n) pipe stages in vhdl
89974: 05/09/30: sarnaths@gmail.com: reading bits using JBits 3.0
89975: 05/09/30: Chris: Virtex-4 FX20 PPC405 Startup Issue
90034: 05/10/03: Florian: Re: Virtex-4 FX20 PPC405 Startup Issue
90042: 05/10/03: Chris: Re: Virtex-4 FX20 PPC405 Startup Issue
90344: 05/10/10: wiggs: Re: Virtex-4 FX20 PPC405 Startup Issue
90346: 05/10/11: Jim Granville: Re: Virtex-4 FX20 PPC405 Startup Issue
90349: 05/10/10: wiggs: Re: Virtex-4 FX20 PPC405 Startup Issue
90380: 05/10/11: <rwightman@gmail.com>: Re: Virtex-4 FX20 PPC405 Startup Issue
90388: 05/10/11: Peter Ryser: Re: Virtex-4 FX20 PPC405 Startup Issue
90592: 05/10/17: Peter Ryser: Re: Virtex-4 FX20 PPC405 Startup Issue
90409: 05/10/12: Chris: Re: Virtex-4 FX20 PPC405 Startup Issue
89977: 05/09/30: Francis: ISE does not initialize the bitstream of a EDK project
89992: 05/10/01: Antti Lukats: Re: ISE does not initialize the bitstream of a EDK project
90027: 05/10/03: Zara: Re: ISE does not initialize the bitstream of a EDK project
89978: 05/09/30: Francis St-Pierre: More than one embedded system in ISE
90026: 05/10/03: Zara: Re: More than one embedded system in ISE
90205: 05/10/06: Francis: Re: More than one embedded system in ISE
90231: 05/10/07: Zara: Re: More than one embedded system in ISE
89980: 05/09/30: Waage: Synthesis with Icarus Verilog
89982: 05/09/30: eeh: VHDL 2 dimension array
89986: 05/10/01: Simon Peacock: Re: VHDL 2 dimension array
89989: 05/10/01: Karthikeyan Subramaniyam: Re: VHDL 2 dimension array
90006: 05/10/02: Simon Peacock: Re: VHDL 2 dimension array
89990: 05/10/01: eeh: Re: VHDL 2 dimension array

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