Python Control System : Create control loops and let the AI set the PID parameters
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Jan 30, 2025 - Python
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control-unit
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Solutions for The Nand Game, a game that teaches the fundamentals of computing by building a computer from scratch.
solutions hardware memory processor computer switching logic-programming logic-gates logic-circuit digital-design binary-logic control-unit arithmetic-logic-unit nandgame fundamentals-of-computing arithmetic-circuits nand-game thenandgame-solutions logic-unit random-access-memory
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Nov 4, 2023
Inverted Pendulum in python with pybox2d. Fuzzy and PID simulation included.
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Jan 24, 2021 - Python
This is an implementation of a simple CPU in Logisim and Verilog.
cpu instructions assembler alu logisim modelsim control-unit cpu-design cpu-simulation register-file data-memory address-memory
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Jan 11, 2019 - Verilog
MiniMIPS | RISC Processor Design | CS39001 Course Project
pipeline processor assembler vivado hardware-designs assembly-language-programming computer-architecture verilog-hdl instruction-set-architecture mips-architecture control-unit fpga-programming controlpath computer-organization-and-design risc-architecture datapath-design
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Sep 14, 2025 - Verilog
Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC UltraTM.
polito vhdl scripts tcl rtl verilog synthesis digital-design control-unit subtractor physical-design booth-multiplier register-file windowed-register-file adder-subtractor
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Jan 24, 2021 - Verilog
🧠 Pipelined Processor is to design, implement and test a Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor.
python state-machine memory processor instrumentation verilog buffers computer-architecture registers program-counter control-unit pipline pipline-operators cufe-2024 execution-unit pipelined-processor
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Oct 16, 2023 - Verilog
A Datapath design which able to execute store operation as memory instruction, substraction and or operations as arithmetic instruction by Logisim. Additional explanations in readme.
instructions datapath alu logisim program-counter control-unit register-file data-memory instruction-memory
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Jun 23, 2021
This project involves designing a single-core RISC-V CPU using Verilog. The design includes an Arithmetic Logic Unit (ALU) with flags, an assembly to machine code converter, a control unit, a microarchitecture and memory initialization to ensure proper functioning of the CPU.
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Oct 11, 2024 - JavaScript
This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.
simulation user-interface computer-architecture instruction-set-architecture code-execution mips-simulator 16-bit-cpu control-unit processor-design cpu-design logic-circuits gui-dashboard custom-processor
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Aug 6, 2024 - JavaScript
fpga memory processor verilog vivado datapath alu verilog-hdl risc-v digital-design control-unit fpga-programming
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Mar 12, 2023 - Verilog
Implementation of a microprogrammed control unit for didactic purpose
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Dec 5, 2017 - C
An automobile taillight control unit I created using VHDL, programmed to run on the Altera Cyclone V board.
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Feb 8, 2021 - VHDL
Software for 3-axis machine control. It uses a Raspberry Pi with motor controllers and additional electronics. Features: visualization, GPIO emulation, touchscreen capability, and Cython optimization. Tested on Windows(visu) and Raspberry Pi OS. Under development with Pyside2 and OpenGl.
visualization python raspberry-pi opengl gpio raspberrypi pyqt5 python3 gui-application pyside2 circuit py 3d wavefront-obj motor-driver diploma-project qt-designer control-unit raspberry-pi-4
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Jul 1, 2023 - Python
18-bit processor implementation using Logisim
finite-state-machine alu logisim instruction-set-architecture circuit-design control-unit processor-design
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Jul 10, 2023 - Python
simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL.
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Jun 5, 2023 - Verilog
from back in the university, a digital design laboratory project, designing a data path and control unit of ram
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Jan 3, 2018
Single Cycle MIPS Datapath implementation in Verilog that extends the standard MIPS architecture with seven custom instructions, featuring a complete processor design with control unit, ALU, register file, and memory components.
processor verilog computer-architecture instruction-set-architecture mips-architecture control-unit datapath-design
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Jun 10, 2025 - Verilog
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Aug 31, 2018
My Solutions to Computer Architecture Course Practical Assignments
cache processor vhdl computer-architecture alu fifo fifo-queue multiplier control-unit direct-mapped-cache
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Sep 2, 2024 - VHDL
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