Verilog

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Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

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logisim-evolution

logisim-evolution / logisim-evolution

Star 6.3k

Digital logic design tool and simulator

education simulator fpga vhdl logic circuits verilog circuit digital-logic logisim digital-circuit digital-circuits timing-diagram digital-logic-design logisim-evolution

Updated Oct 14, 2025
Java

LeiWang1999 / FPGA

Star 5k

帮助大家进行FPGA的入门,分享FPGA相关的优秀文章,优秀项目

fpga verilog xilinx vivado pynq

Updated May 15, 2022

chisel

chipsalliance / chisel

Star 4.4k

Chisel: A Modern Hardware Design Language

scala chip-generator chisel rtl chisel3 firrtl verilog

Updated Oct 15, 2025
Scala

openwifi

open-sdr / openwifi

Star 4.4k

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

linux fpga zynq hls hardware wifi verilog xilinx sdr analog-devices ieee80211 xilinx-fpga dma software-defined-radio ofdm csma ad9361 802-11 mac80211 openwifi

Updated Sep 23, 2025
C

verilator

verilator / verilator

Star 3.1k

Verilator open-source SystemVerilog simulator and lint system

cpp rtl verilog compilers systemc system-verilog verilator verilog-simulator

Updated Oct 15, 2025
C++

SpinalHDL / VexRiscv

Star 2.9k

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga vhdl riscv verilog soc spinalhdl softcore

Updated Oct 16, 2025
Assembly

SI-RISCV / e200_opensource

Star 2.8k

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

cpu core verilog china nuclei risc-v ultra-low-power

Updated Mar 24, 2021
Verilog

darklife / darkriscv

Star 2.4k

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

fpga core riscv verilog risc-v

Updated Jul 16, 2025
Verilog

The-OpenROAD-Project / OpenROAD

Star 2.2k

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

cpp tcl eda rtl verilog def gdsii timing-analysis openroad lef opendb-database

Updated Oct 16, 2025
Verilog

jbush001 / NyuziProcessor

Star 2.1k

GPGPU microprocessor architecture

processor-architecture fpga hardware gpu graphics verilog microprocessor gpu-computing

Updated Nov 8, 2024
C

cocotb / cocotb

Star 2.1k

cocotb: Python-based chip (RTL) verification

python test vhdl verification verilog uvm

Updated Oct 16, 2025
Python

SpinalHDL / SpinalHDL

Star 1.9k

Scala based HDL

scala fpga vhdl rtl verilog

Updated Oct 13, 2025
Scala

pConst / basic_verilog

Star 1.9k

Must-have verilog systemverilog modules

spi-interface fpga hls encoder delay tcl verilog debounce xilinx synchronizer uart altera uart-verilog fifo pwm uart-protocol spi-master uart-controller uart-tx uart-receiver

Updated Aug 2, 2025
Verilog

icestudio

FPGAwars / icestudio

Star 1.8k

❄️ Visual editor for open FPGA boards

javascript editor fpga ide blocks verilog icestorm lattice icestudio

Updated Aug 19, 2025
JavaScript

analogdevicesinc / hdl

Star 1.8k

HDL libraries and projects

fpga verilog hdl hacktoberfest analog-devices jesd204b

Updated Oct 16, 2025
Verilog

serv

olofk / serv

Star 1.7k

SERV - The SErial RISC-V CPU

asic fpga verilog risc-v

Updated Oct 15, 2025
Verilog

riscv-mcu / e203_hbirdv2

Star 1.6k

The Ultra-Low Power RISC-V Core

cpu fpga core riscv verilog china hummingbird nuclei soc risc-v low-power e203

Updated Aug 6, 2025
Verilog

The-OpenROAD-Project / OpenLane

Star 1.6k

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.