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The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds

Updated Sep 15, 2025
Python

limbo018 / DREAMPlace

Deep learning toolkit-enabled VLSI placement

deep-learning pytorch gpu-acceleration vlsi vlsi-physical-design vlsi-placement

Updated Sep 27, 2025
C++

OpenTimer / OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

parallel-computing eda circuit-simulator cad verilog cpp17 circuit-simulation vlsi circuit-analysis computer-aided-design vlsi-physical-design sta electronic-design-automation vlsi-circuits static-timing-analysis

Updated Jul 7, 2025
Verilog

VLSI-EDA / PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

python asic fpga simulation vhdl verification xilinx synthesis regression-testing altera hardware-designs lattice hardware-libraries poc-library vlsi testbenches hardware-modules osvvm uvvm vunit

Updated Jul 30, 2025
VHDL

efabless / openlane2

The next generation of OpenLane, rewritten from scratch with a modular architecture

flow asic eda verilog vlsi pnr silicon lvs flows sta gdsii drc pdk openroad openlane sky130 gf180mcu rtl-to-gds

Updated Feb 26, 2025
Python

arm-university / VLSI-Fundamentals-Education-Kit

Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor

arm computer-engineering hardware-designs vlsi electrical-engineering cadence-virtuoso microprocessor-implementation synopsys-design devices-circuits-materials

Updated May 30, 2025
HTML

DegateCommunity / Degate

A modern and open-source cross-platform software for chips reverse engineering.

security multi-platform gui cross-platform cpp vhdl reverse-engineering cybersecurity verilog chips vlsi security-tools

Updated Nov 25, 2024
C++

nitram2342 / degate

Open source software for chip reverse engineering.

visualization gui library vhdl reverse-engineering image-processing verilog chip image-recognition vlsi

Updated Sep 22, 2020
C++

AUCOHL / DFFRAM

Standard Cell Library based Memory Compiler using FF/Latch cells

verilog vlsi vlsi-physical-design vlsi-circuits electronics-design asic-design

Updated Oct 4, 2025
Verilog

cuhk-eda / Xplace

Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization

gpu eda gpu-acceleration vlsi placement physical-design timing-driven routability-driven

Updated Jun 19, 2025
C++

eelab-dev / EEcircuit

A browser-based SPICE circuit simulator

simulation electronics webassembly wasm spice emscripten circuit vlsi cmos ngspice webgl-plot

Updated Oct 12, 2025
TypeScript

purdue-onchip / gds2Para

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

parse eda vlsi integrated-circuits interconnect gdsii spef electronic-design-automation vlsi-circuits

Updated Apr 23, 2023
C++

phoeniX-Digital-Design / phoeniX

A Reconfigurable RISC-V Core for Approximate Computing

cpu fpga embedded-systems riscv microprocessor computer-architecture vlsi risc-v approximate-computing cpu-design

Updated May 30, 2025
Verilog

asyncvlsi / act

ACT hardware description language and core tools.

language eda circuit-simulator cad dataflow chp dataflow-programming prs hdl vlsi hardware-description-language production-rules design-automation asynchronous-circuits vlsi-cad asynchronous-vlsi communicating-hardware-processes

Updated Oct 14, 2025
C++

antonblanchard / vlsiffra

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

verilog booth vlsi adder multiplier physical-design dadda amaranth-hdl

Updated Sep 20, 2023
Python

drec-fpga-intro

viktor-prutyanov / drec-fpga-intro

Материалы для курсов по проектированию цифровых вычислительных систем

education asic fpga verilog vlsi risc-v

Updated Oct 13, 2025
Verilog

NTU-LaDS-II / FAN_ATPG

FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool

cli cpp eda lex verilog yacc vlsi fan-out atpg electronic-design-automation fault-simulation sequential-circuits stuck-at combinational-circuits test-pattern vlsi-testing

Updated Jul 2, 2025
Verilog

hsluoyz / Atalanta

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

verilog vlsi atalanta atpg

Updated May 7, 2024
Verilog

luckyrantanplan / nthu-route

VLSI EDA Global Router

router eda vlsi vlsi-physical-design electronic-design-automation vlsi-circuits globalrouter ispd lattice-graph multi-maze-routing

Updated Jan 22, 2018
C++

ahmed-agiza / EDAViewer

EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!

webgl serverless hardware viewer layout eda server-side-rendering cgo pixijs vlsi opendb def digitaldesign electronic-design-automation physical-synthesis lef opendb-database serverless-side-rendering hardware-design def-viewer

Updated Jan 6, 2023
JavaScript

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