Various HDL (Verilog) IP Cores

• Updated Jul 1, 2021
• Verilog

VUnit is a unit testing framework for VHDL/SystemVerilog

• Updated Nov 20, 2025
• VHDL

Python-based Hardware Design Processing Toolkit for Verilog HDL

• Updated Jun 15, 2024
• Python

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

• Updated Sep 16, 2025
• Verilog

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

• Updated Oct 17, 2023
• Python

HDL support for VS Code

• Updated Nov 24, 2025
• TypeScript

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

• Updated Aug 10, 2024
• Python

High throughput JPEG decoder in Verilog for FPGA

• Updated Mar 5, 2022
• Verilog

Image Processing Toolbox in Verilog using Basys3 FPGA

• Updated May 20, 2025
• VHDL

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

• Updated Jun 20, 2024
• Verilog

A complete open-source design-for-testing (DFT) Solution

• Updated Aug 30, 2025
• Swift

A simple implementation of a UART modem in Verilog.

• Updated Nov 10, 2021
• Verilog

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous F...

• Updated Jan 29, 2024
• Verilog

5-stage pipelined 32-bit MIPS microprocessor in Verilog

• Updated Apr 3, 2020
• Verilog

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

• Updated Jul 31, 2022
• Verilog

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

• Updated Dec 29, 2024
• Verilog

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

• Updated Jul 9, 2023
• Verilog

2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)

• Updated May 26, 2019
• Verilog

中山大学计算机组成原理实验 (2018 秋):用 Verilog 设计并实现的简易单周期和多周期 CPU

• Updated Mar 21, 2021
• Verilog

JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.

• Updated Oct 19, 2025
• SystemVerilog