97 questions
- Bountied 0
- Unanswered
- Frequent
- Score
- Trending
- Week
- Month
- Unanswered (my tags)
0
votes
0
answers
71
views
How to setup approriate configs for single-core rocket-chip Gemmini Accelerator?
I'm buiding a single-core rocket chip, which use an Gemmini interface to do systollic array, and I use board Arty-Z7 to run demo on FPGA. My problem here is I don't know how to choose a suitable ...
0
votes
0
answers
58
views
What is the maximum outstanding in Bus interface?
I am wondering what the maximum outstanding is and how to calculate the maximum outstanding number.
Especially, for the case of AXI interface, how to know the maximum outstanding? Is it usually just ...
0
votes
1
answer
265
views
Starting a firmware on imx7d m4 core with bootaux, on u-boot, fail when using TCM memory but not when using DDR memory
I want to load a firmware on the imx7d M4 core.
I am using a colibri imx7d-eMMC (MCIMX7D5EVM10S) SoC with a yocto linux build installed which include u-boot bootloader (details below).
When I load the ...
0
votes
0
answers
185
views
How to send windows logs to LogRhythm DP using Microsoft Sysmon?
I want to transfer windows logs to LogRhythm SIEM, but I can't use logRhythm agent because it uses the PORT 445 which I don't want to open.
I want to use Microsoft Sysmon. How to use it and which PORT ...
0
votes
1
answer
75
views
LoanIO from HPS to FPGA get analog signals,cycloneVsoc dev kit,selfmade RTOS
I’m working on a board that is a cycloneVsoc dev kit. The board has a simple RTOS program that I wrote.
Because the FPGA on the board does not have an external PIO interface, I used LoanIO to borrow ...
2
votes
0
answers
161
views
How to get two separate cores the same IRQ signal and let them do different work
I'm using a SOC baremetal system based on CycloneV SX with ARM based CortexA9 Dual Core HPS inside.
To ensure the synchronization of the two cores in the dual-core system, I use a 50us timer interrupt....
0
votes
0
answers
38
views
FPGA Parallel output timing to satisfy input timing
Let's say a FPGA reads flip-flop D and outputs Q on the second rising edge of a CLK (figeure1). How can this satisfy the input setup time [TpdSU] of another device (figure2)?
Do they generally not use ...
0
votes
1
answer
405
views
Vivado verilog 1 LUT cells form a combinatorial loop
I'm facing around 100 errors related to combinatorial loops when bitstreaming.
The signals causing these errors are addr_121f, addr_store_1_f, and addr_store_2_f.
I'm having difficulty understanding ...
0
votes
1
answer
167
views
How to find BOOT-SEL GPIO PIN?
I'm new to embedded linux and trying to explore it using Allwiner T113-i EVB.
Right now I'm struggling with boot process.
According to user manual BROM of SoC will try fetch boot code from SD card if ...
-2
votes
1
answer
630
views
FIFO Depth Calculation
I have 2 blocks, out of which block_A is writing and block_B is reading.
Writing configurations : 3 writes per 5 clocks,
Reading configurations : 30 reads per 50 clocks
What is the required FIFO depth ...
1
vote
0
answers
485
views
is it possible to connect two PCIe endpoint directly for just high-speed comunnication purpose?
I'm currently trying to design a system where two identical SoC chips interact with each other.
I want to read and write each other's chip memory using PCIe.
As far as I know, since the two chips are ...
0
votes
1
answer
341
views
vim/gvim can not highlight .svh/.sv/.txt file automatically
I would like to use vim/gvim to automatically highlight my code file for example .svh/.sv/.txt file and here is my setting picture:
and i source it. But it always failed to automatically highlight ...
1
vote
1
answer
446
views
To configure pin define in a SoC, what's different between doing it in U-Boot and Linux Device Tree?
As my knowledge about the booting flow of a (embedded) Linux platform, there's a bootloader (e.g. U-Boot) running on the CPU first, then load the Linux kernel into memory.
While both U-Boot and Linux ...
0
votes
3
answers
914
views
How can I link Systick_Handler() to the exception of Systick?
I am doing some programming on Arm Cortex M0 by C without any built-in libraries. I want to make a timer based on Systick and there is my code.
void systick_enable(void){
SYSTICK_BASE -> CSR = ...
0
votes
0
answers
214
views
Can an MMU and MPU conflict with each other?
In the AM5K2E02 System-on-Chip, there is an MMU (memory management unit) in the core, and also a peripheral device MPU (memory protection unit).
On other pages, the MMU is described as a superset of ...