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Trouble Capturing Audio from INMP441 MEMS Microphones via I2S on Tang Nano 9K FPGA
i’m working on a project where I’m reading two INMP441 MEMS microphones that share the same I2S lines. I’ve connected one microphone’s LR pin to VCC and the other to GND, so they correspond to left ...
Advice
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1
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21
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How to use FixedPoint16 for DNNs on FPGAs?
I am trying to design an accelerator on an FPGA to compute convolutional layers in CNNs? For now, I use INT16 as input, normalized to the range [0,1) and quantized to Q1.15. Same for weights, but with ...
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1
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Timing of a I2C state machine on an FPGA
I’ve realized that my understanding of I2C timing is weaker than I thought. I’ve read the datasheet for the component I’m working with, but I’m still struggling to understand how to properly time my ...
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2
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83
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I2C implementation aid on FPGA board
I’m working on implementing an I2C master in VHDL on an FPGA, and I’ve run into a problem with generating the STOP condition. Everything else in the transfer appears correct, but the STOP condition ...
2
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2
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104
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Proper way of resetting a FSM
I usually work with Xilinx FPGA boards. Based on the documentation I've reviewed and the research I've done, I try to avoid using a global reset signal in my designs as much as possible. However, let'...
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1
answer
157
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Difference between signal and variable in VHDL (FPGA hardware perspective, not just simulation)
I understand the usual textbook difference between signal and variable in VHDL:
variable := updates immediately inside a process
signal <= updates after a delta cycle
variables are local, ...
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0
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62
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AXI DMA Linux Driver on ZynqMP
I have a ZynqMP board with 4GB of PS RAM and 2GB of PL RAM. I have to write stream data to PL RAM using the AXI DMA s2mm channel and transmit it through 1G Ethernet. I've done this in a bare metal ...
2
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1
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93
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Why is my simple ARM7 data memory on Verilog failing tests?
I'm implementing a simple ARM7 in Verilog and am currently in the process of creating a simple data memory. I've come up with something like this:
// very simple sdata implementation with 1mb~ memory
...
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37
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How to resolve license check error when using rfnoc_image_builder to build fpga image
The build failed at 'Adding block description from license_check.yml' as shown below in bold
# Snapshot of build
blackvoid@blackvoid:~$ rfnoc_image_builder -F $UHD_FPGA_DIR -I $RFNOC_OOT -y $RFNOC_OOT/...
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71
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How to setup approriate configs for single-core rocket-chip Gemmini Accelerator?
I'm buiding a single-core rocket chip, which use an Gemmini interface to do systollic array, and I use board Arty-Z7 to run demo on FPGA. My problem here is I don't know how to choose a suitable ...
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FTDI Communication Problem with Pylibftdi on a Windows Machine
I have a Digilent Nexys Video Artix-7 FPGA development board. This board has two Micro USB ports. One is used for UART-USB communication, and the other one for uploading bitstreams(as a JTAG). I ...
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programming DDR to produces samples for RFSOC4x2 question
This is programming FPGA question so its both programming in C and hardware.Hope its suitable for this forum and If not I'll be glad to get a more suitable place to post this question.
I am building a ...
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1
answer
86
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In a System Verilog FSM can a repetitive State be converted to a Task?
I'm writing an FPGA state machine in System Verilog to read bytes from a SPI port and parse them into commands to the FPGA. The "RXSPIBITS" state is used to read SPI bytes by multiple other ...
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72
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How to fix State <name> contains multiple transitions, but more than one transition equation are TRUE when <text> in Quartus?
I'm trying to develop a Elevator FSM machine in quartus in order to get his equivalent to HDL code. The FSM is this:
But when I set the Input, transitions and output in "State Machine Wizard&...
1
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1
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109
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Should UVM testbench work with pre-synthesis or post-synthesis FPGA code? [closed]
I’m working on an FPGA project and planning to use UVM (Universal Verification Methodology) for verification. I’m confused about the timing of when to apply UVM in the design flow.
Should I develop my ...