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-1
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1
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95
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What's point of port to port type of connection in TLM? [closed]
In UVM TLM1, there are three main interface types:
port — the initiator of a transaction,
export — a proxy that forwards port requests to an implementation,
imp — the implementation, which contains ...
1
vote
1
answer
109
views
Should UVM testbench work with pre-synthesis or post-synthesis FPGA code? [closed]
I’m working on an FPGA project and planning to use UVM (Universal Verification Methodology) for verification. I’m confused about the timing of when to apply UVM in the design flow.
Should I develop my ...
1
vote
1
answer
154
views
Why does APB testbench not send data into the prdata register?
Here is my code on EDA Playground.
`include "uvm_macros.svh"
import uvm_pkg::*;
//////////////////////transaction class//////////////////////
class transaction extends uvm_sequence_item;
`...
1
vote
1
answer
543
views
How to print topology in UVM?
I am trying to use the print topology command in our UVM environment, but I keep getting this error message.
The 1st error message is:
xmvlog: *E,NOSYM (testName.svh,50|19): uvm_top could not be ...
0
votes
1
answer
99
views
`define value assignment to a string
I am writing some SV code. I have 'define value which I want from terminal with +define for following `define ENV_TOP. the value should go in the config_db block as I am retrieving the value for ...
1
vote
1
answer
108
views
Does SystemVerilog have a log package that allows fine control over log messages?
VHDL has OSVVM and VUnit that provide log packages. One can create different levels for log messages by assigning numerical values with names. Higher value means message is more important. Then a ...
1
vote
1
answer
83
views
ERROR VCP2000 "Syntax error. Unexpected token: initial." "testbench.sv" 50 7
I am not able to find the exact reason for the error here. Can anyone help me?
`include "uvm_macros.svh"
import uvm_pkg::*;
class my_driver extends uvm_driver;
`uvm_component_utils(...
2
votes
1
answer
121
views
In UVM can we override base_test with base1_test ? with everything else remaining same?
I have a testbench with 10s of tests(files) that derive from my 'base_test' (base_test extends uvm_test).
say I add a special mode 'base_1_test', where 'base_1_test' is derived from 'base_test'. Now ...
1
vote
1
answer
284
views
UVM testbench for APB driver run_phase logic
In the driver_class run_phase code below, I am not able to understand how to write the logic to send the transaction to the DUT.
Can we give Penable, Psel, Pready values manually in the driver class ...
1
vote
2
answers
683
views
How to randomize a variable in system verilog only if it's not having a default value
I want to have a class where I want to put all of the rand variables with some default value which should be only randomized if they are assigned non-default value from their handle
Example
typedef ...
0
votes
1
answer
625
views
UVM enforce clocking block usage
I want to use the following SystemVerilog concepts:
clocking block: to avoid race conditions between driver and monitor, i want to have it in a central place, in the interface
modport: normally (e.g. ...
-2
votes
1
answer
369
views
Regarding Configdb set and get issues in UVM
My question is when i am doing set in my_test class and get in componentA class, however get is causing issue since i am trying to assign compA instance names i.e compA[0] compA[1] to be assigned to ...
0
votes
1
answer
283
views
Is it better to use uvm_reg_file for an array of uvm_reg objects or just declare an array in a uvm_reg_block?
I am trying to justify using uvm_reg_file but that will add an extra layer of hierarchy than if I just declare an array of the "uvm_reg" object inside the uvm_reg_block class.
I don't expect ...
1
vote
1
answer
749
views
UVM agents - single/multiple?
I want to test a receiver with the following ports:
Details about the arrows in the diagram above:
Control/Status Registers:
16x32bit input signals (16 control registers)
16x32bit output signals (...
-1
votes
1
answer
268
views
UVM RAL: NULL pointer is dereference
I am a beginner in using UVM RAL. I am trying to access by DUT Registers using UVM_BACKDOOR. I think this should not require an adapter and a predictor. I maybe wrong thinking so.
Below is my code ...