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1 vote
1 answer
154 views

Here is my code on EDA Playground. `include "uvm_macros.svh" import uvm_pkg::*; //////////////////////transaction class////////////////////// class transaction extends uvm_sequence_item; `...
1 vote
0 answers
357 views

I'm trying to index into a 2D array in Verilog like this: `include "src/elementwise_multiplication.v" module parallel_elementwise_multiplication_dynamic #(parameter N = 8, parameter M = 2) ( ...
1 vote
1 answer
370 views

I have been trying to open EPWave at EDA playground, and it always returns the error: No *.vcd file found. EPWave will not open. Did you use '$dumpfile("dump.vcd"); $dumpvars;'? I have ...
1 vote
2 answers
305 views

I am trying to implement an array Right Shifter. It accepts an array of integers, then right shifts everything to the right-side of specified index position, and inserts a specified integer value at ...
1 vote
1 answer
115 views

module IIR_filter(xn, clk, rst_n, yn); input signed [3:0]xn; input clk,rst_n; output reg signed [3:0]yn; reg signed [3:0]y_1,y_2,x_1,x_2,x_3; always @(*)begin yn = xn - (x_1) + (x_2) +...
0 votes
1 answer
85 views

When I run this code to EDAplayground, it will give me an error of: Finding VCD file... No *.vcd file found. EPWave will not open. Did you use '$dumpfile("dump.vcd"); $dumpvars;'? //Verilog ...
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0 votes
1 answer
947 views

I am trying to run the following VHDL code for a digital clock, but I am encountering an error message and I am not sure how to fix it. This is the link to my code in EDA Playground library IEEE; use ...
1 vote
1 answer
890 views

I'm trying to compile a small UVM verification environment in EDA playground. I'm getting this error: EDA playground ERROR VCP5294 "Undefined package uvm_pkg. The code attached below: import ...
0 votes
1 answer
432 views

Case statement choices cover only 6 out of 10 cases for my vending machine code I am getting this error after execution of my very long program in VHDL. However its said that When others => can be ...
1 vote
1 answer
2k views

I've typed a design code and a testbench code for inverter circuit. The input is of 4 bits, and so is the output. I've tried to display the waveform using: $dumpfile("dump.vcd"); $dumpvars(...
-1 votes
1 answer
421 views

I am facing with problems with VHDL with EDA playground - Any solutions are welcomed. design.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith....
3 votes
2 answers
1k views

When using typedef to declare a user-defined type, both these forms are accepted by EDA Playground: typedef reg[4:0] reg5; typedef logic[4:0] logic5; However, if doing something similar based on wire ...
0 votes
2 answers
290 views

I was learning about loops in Verilog and wanted to create a simple clock with time period of 20ns. I am getting the error below whenever I am trying to run the code in EDA Playground. module Pulse(...
1 vote
2 answers
4k views

I am trying to execute code @ https://www.edaplayground.com/x/e2Pe. The code seems to be error free. However, when trying to simulate with VCS tool, it is giving me below error: UVM_ERROR: set: unable ...
-1 votes
2 answers
761 views

Hello I am getting the above error for the subscriber class I created as following: The error seems in the write function of the class but I am not sure what I am missing in the function. `...

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