239 questions
- Bountied 0
- Unanswered
- Frequent
- Score
- Trending
- Week
- Month
- Unanswered (my tags)
1
vote
2
answers
140
views
verilog LRM 23.3.3.1 connecting output to output
From the LRM:
23.3.3.1 Port coercion A port that is declared as input (output) but used as an output (input) or inout may be coerced to inout. If not
coerced to inout, a warning shall be issued.
The ...
2
votes
1
answer
79
views
Unexpected results in fixed-point conversion in Verilog
Why regA and regB have two different values, while regC and regD work as I would expect?
reg signed [31:0] regA;
reg signed [31:0] regB;
reg signed [15:0] regC;
reg signed [15:0] regD;
initial begin
...
-1
votes
2
answers
135
views
Verilog clock implementation gone wrong
I just started learning Verilog and made a system clock and its respective testbench, but it is getting stuck in an infinite loop in the testbench. Could you please help me?
Below is the ...
1
vote
2
answers
128
views
Verilog assignment using vectors
I am attempting to assign data from one wire to another wire in Verilog using vector subscripting. This is the simplest implementation that I could think to write to demonstrate the problem I have. ...
1
vote
2
answers
466
views
How to select bits in expression?
This my excersize is make a 6-to-64 decoder using 3-to-8 decoder. I've implemented it as below:
module dec_3_8 (
input wire [2:0] in,
output wire [7:0] out,
input en
);
genvar i;
generate
...
-1
votes
1
answer
354
views
D-type Flip Flop - Behavioral vs Gate-Level Modeling in Verilog, Timing of state transitions
Modeling a D-type Flip Flop in Verilog with gate-level modeling vs. behavioral modeling seems to result in state transitions happening at different edges of the clock signal. I'm sure I'm missing ...
1
vote
2
answers
150
views
Not sure why the method "name" is not available
I was trying to understand better how enums and standard methods work.
I compile the code with iverilog -g 2012 example.sv in Icarus Verilog version 11.0 (stable).
I get the error sorry: Enumeration ...
1
vote
2
answers
138
views
for loop unrolling not working as expected
I have a module with some parameters. Those are used in a for loop that I would have thought would unroll the contents. In the end, there would be no for loop or index, just a big list of repetitive ...
0
votes
1
answer
640
views
Creating a ".vvp" file in verilog (using vsCode)
I've been trying to compile a ".v" file into a ".vvp" file but, when i code and run in terminal, i doesn't run. Here the module code, test bench code and the terminal code:
//...
0
votes
1
answer
754
views
Icarus Verilog Syntax error "I give up" for NAND gate
I am getting the error message below.
./nand.v:1: syntax error
I give up.
Here is my nand.v code:
module nand (A, B, C);
input A, B;
output C;
assign C = ~(A & B);
endmodule
And ...
1
vote
0
answers
357
views
Array slices are not supported for continuous assignment
I'm trying to index into a 2D array in Verilog like this:
`include "src/elementwise_multiplication.v"
module parallel_elementwise_multiplication_dynamic #(parameter N = 8, parameter M = 2) (
...
1
vote
1
answer
75
views
Matrix Multiplication Testbench Yields Inconsistent Results
I'm using iverilog with -g2012 flag to compile the following matrix multiplication code and testbench:
`timescale 1ns / 1ps
module testbench();
// Testbench parameters
parameter m1 = 2;
parameter n1 ...
1
vote
1
answer
370
views
No .vcd file found error, but I have used the $dump code
I have been trying to open EPWave at EDA playground, and it always returns the error:
No *.vcd file found. EPWave will not open. Did you use
'$dumpfile("dump.vcd"); $dumpvars;'?
I have ...
1
vote
1
answer
106
views
How to use ripple adder for addition in shift and add binary Multiplier?
module bin_mult(
output reg [7:0]mult,
output reg [1:0]count,
output carry,
input [3:0]a,b,
input clk,load);
reg enable;
reg [7:0]sum;
reg [3:0]m[3:0];
//reg [1:0]...
0
votes
1
answer
284
views
How do I fix error in vs code: " Wrong number of ports. Expecting 8, got 7."
I'm trying to make a 1:4 Demultiplexer but I keep getting the error about my ports. Every time I try and type the command
iverilog -o Lab12_tb.vvp Lab12_tb.v
to simulate my text bench in the vs code ...