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1
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1
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103
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Why are latches inferred in my FSM design despite driving all signals in every state?
I'm working on a FSM design in Verilog and getting inferred latches during synthesis in Synopsys Design Vision. Below is the Verilog code for my FSM:
// control path
//control path
always @(*) ...
1
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1
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54
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SystemVerilog not reading data correctly
The data read from A_arr, B_arr and C_arr are incorrect.
The value I have in Moddelsim is not what I defined in the testbench.
I have a testbench for my design. It should fetch inputs from A_arr and ...
-1
votes
1
answer
118
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Register increments twice within a non blocking always
I want to do an up-counter which has an output enable (when high the up-counter is supposed to count up at each clock cycle, otherwise it keeps its previous value). In order to achieve visible results ...
0
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2
answers
309
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How to initialize coefficients of a large digital filter in Verilog?
I am trying to make a synthesizable filter in verilog. I have the fixed-point filter coefficients in a text file. I am looking for an elegant and scalable way to pass on these filter coefficients. The ...
0
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1
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213
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How can I avoid glitches in behavioural vhdl code simulations? [closed]
I've been trying to write VHDL code for a counter.
Ultimately, I would like to take the output value, check it with a constant value, and see if the counter has reached the constant value. if it ...
-2
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1
answer
630
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FIFO Depth Calculation
I have 2 blocks, out of which block_A is writing and block_B is reading.
Writing configurations : 3 writes per 5 clocks,
Reading configurations : 30 reads per 50 clocks
What is the required FIFO depth ...
0
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0
answers
108
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Function Wash not increasing value in sec signal in VHDL
I'm very new to VHDL and for my digital design project I have to make a simulation of a washing machine in a DE10-Lite FPGA with finite states.
Everything seems good so far but when it's turn for the ...
0
votes
1
answer
388
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1 bit comaparator using 2x1 mux ? Create First 1 bit magnitude comparator and implement on mux?
I know What is the comparator but i don't know how to implement with Mux
Please Give Answer Of Hoe to Design 1 bit comaparator using 2x1 mux, I Create First 1 bit magnitude comparator in this we have ...
1
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1
answer
254
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Why do I get run time fatal error - Range width expression must be positive - for my up counter design?
I am trying to design a 17-bit ripple up counter using a positive edge triggered d flip flop in my design. Here is my code:
`timescale 1us/ 1ns
module upcounter (clk, pr, clr, out);
input wire ...
1
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1
answer
54
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how to add in binary
I don't understand when 100 appear in add what I should do. what the carry for the next step? They are marked with red and blue colors
2
votes
1
answer
240
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Why do we have to add a "clr" (clean input wire) while forming a T flip-flop in Verilog with Vivado?
I am trying to form a T flip-flop in Verilog. I am studying verilog from "Digital System Design with FPGA: Implementation using verilog and vhdl" and the code for T flip-flop is here below:
...
0
votes
1
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139
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Writing A'B'CD+ABC' using two inverters and 5 2:1 multiplexers
The question says draw F(A,B,C,D)=∑(3,7,11,12,13). I derived A'B'CD+ABC'. I am trying to draw it using two inverters and 5 2:1 multiplexers but i couldn't connect the output to the separate components ...
1
vote
2
answers
649
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Continuous assignment with 0 delay not getting the expected value after a signal positive edge
I have implemented an 8 bit serial-in parallel-out register in SystemVerilog and I'm trying to test it. I'm using Icarus Verilog as simulator.
In the test bench, I send 8 bits and wait for the rising ...
0
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2
answers
241
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What are buffers used for in the construction of the D latch?
I am reading a book Digital Design and Computer Architecture and in the chapter on the D trigger at the transistor level it says "A compact D latch can be constructed from a single transmission ...
1
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1
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1k
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JK-Flip Flop: K-Map to find the Value of Next State (Qn+1)
Given the Truth Table, Characteristic Table and Excitation table for a JK Flip Flop. I am doing a K-Map to find Qn+1 (next state) given J, K and current State. The K-Map from a tutorial explaining ...