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0
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2
answers
100
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Natural number not overflowing in Aldec ActiveHdl
Getting a runtime error_0067 Value -1 out of range (0 to 7). Buf_ptr is set as a natural number but still goes negative because it is not overflowing back to 7. This can easily be fixed with an if ...
1
vote
1
answer
256
views
Why do I get run time fatal error - Range width expression must be positive - for my up counter design?
I am trying to design a 17-bit ripple up counter using a positive edge triggered d flip flop in my design. Here is my code:
`timescale 1us/ 1ns
module upcounter (clk, pr, clr, out);
input wire ...
1
vote
1
answer
129
views
Why are modules not connected to each other?
I have to do Verilog coding in Active HDL 12, but I do not know why the three modules do not connect to each other in the top module.
top module
`timescale 1 ns / 1 ps
module Main (Mx1,Mx2,Mx3,Mx4,My);...
0
votes
0
answers
703
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VHDL testbench code not showing output result of 1bit fulladder
here code some warning but no errors found but test bench of this fulladder output waveform sum and carry not showing. there shown u in the carry and sum output, but not inputs are fine only sum and ...
0
votes
1
answer
2k
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I have the following errors appearing on my code, I don't know what they mean neither know how to fix them
So I am trying to write the VHDL for a 32-bit ALU on EDA PLayground, but I get some error messages that I don't quite get, and I don't know how to fix them, can someone please help?
I cannot ...
1
vote
1
answer
7k
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Function to_hstring from std.textio is not working [VHDL]
I tried to run some code from Stack Overflow (How to write an integer to stdout as hexadecimal in VHDL?) and it turned out that to_hstring doesn't work (Even though std library is standard for VHDL). ...
0
votes
1
answer
573
views
High impedance signal does not enter the test bench [VHDL]
First of all, I am new to VHDL and I was trying to create a RAM model (or something similar). The model works fine and I started building my test bench, but it does not reproduce the behavior of the ...
0
votes
1
answer
177
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cocotb simulation with Aldec
I am doing some EDA tools test with cocotb as a testbench. I am running simulations with icarus and verilator without problem, however, with Aldec I have got a problem at "runsim.tcl".
The output of ...
0
votes
1
answer
2k
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Verilog and condition for Always block
Im working on a project and after chasing down a bug i narrowed it down to it being caused by an Always block that doesnt trigger correctly.
module Counter(start,clk_len,done,clk,reset);
...
1
vote
1
answer
250
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Output array won't take the value of an array register
In a simple module I have defined a 4-bit array register, and I use it to assign a value to a 4-bit array output. The output acts like a 1-bit wire even if it has been defined as a 4-bit array.
`...
1
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1
answer
1k
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MachX03 library error in Active-hdl for fpga simulation
edit: I just reinstalled lattice diamond and the updates, Active-hdl was installed automatically, but the simulation still gives me the same error. when i change library machXO3; use machXO3.all; to ...
0
votes
1
answer
535
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My outputs in 4bits fullAdder are always z and don't change
I'm writing 4 bits full adder with verilog in Active-hdl I think my code and test-bench are right but the value of sum and cout are always z in waveform can anybody help me what the problem is.this my ...
3
votes
0
answers
614
views
Signal initialization VHDL
I have an entity which has this
TEMPERATURE: in STD_LOGIC_VECTOR(7 downto 0);
as one of the inputs and I need a signal that has the initial value TEMPERATURE.
In the entity architecture I've declared ...
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user9785232
0
votes
0
answers
184
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PS2 Keyboard interface runs smoothly in Active-HDL simulator, but not working on Nexys2 Board
I have to make a PS2 Keyboard Controller project at the university and i encountered a few problems when trying to test the system on the FPGA board.
It had worked perfectly in the simulator of ...
-1
votes
1
answer
771
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How to find frequency of a clock divider ?
Supposing i have on my board a 100Mhz clock and the following clock divider:
entity div is
port(clk:in std_logic;
clk_out:out std_logic);
architecture ar of div is
begin
process(clk)
variable ...