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5
votes
1
answer
175
views
How to handle strict FIFO waiters with futex when a waiter crashes?
I’m building a shared-memory, event-driven allocator on Linux with:
Multiple producers, single consumer (MPSC)
Variable-size allocations from a shared memory pool
When memory is unavailable, ...
0
votes
0
answers
34
views
How to implement FIFO queue operations in DolphinDB similar to Python’s deque?
In Python, we can use collections.deque to implement FIFO queue operations. For example:
from collections import deque
queue = deque([1, 2, 3])
print("Initial queue:", queue) # ...
0
votes
1
answer
51
views
Unable to integrate JIRA automation with AWS SNS FIFO Topic
I’m currently unable to integrate JIRA Automation with my AWS SNS FIFO topic. Previously, the integration worked fine when using a standard SNS topic. However, after switching to a FIFO topic, the ...
0
votes
0
answers
73
views
Amazon SQS FIFO Consumer Stops Processing Events Until Restart
I am using Amazon SQS FIFO to process events received from a Salesforce subscription. Each event contains a recordId, and we use it to call the Salesforce API to fetch additional details before ...
1
vote
0
answers
78
views
I can not read the FIFO of Semtech SX1231
#include <stdint.h>
#include <stdbool.h>
#include <reg_mg82f6d64.h>
#define RegFifo 0x00
#define RegIrqFlags1 0x27
#define RegIrqFlags2 0x28
void wrb(uint8_t dat);
...
1
vote
1
answer
186
views
Issues with FIFO Implementation – Incorrect Data Read & Flag Behavior
I'm working on a 4-depth, 8-bit wide FIFO in SystemVerilog. I’ve written both the FIFO module and the testbench, but I’m encountering unexpected behavior in data read operations and flag updates.
...
1
vote
1
answer
81
views
How to read from a full named pipe in C to check how many bytes need to be read before writing again?
I have an assignment to:
a) check the capacity of a named pipe (FIFO)
b) check how many bytes I need to read from a full pipe before writing again.
My code successfully writes into the pipe until it ...
0
votes
1
answer
169
views
Fifo initialization and data transmission in Vitis
I have a relatively simple design, and I’ve attached the diagram below. In short, it’s meant to perform a loop where one core sends data to the FIFO, and another core initializes the DMA and waits to ...
1
vote
0
answers
68
views
Lua functions for conky doesn't update independently
I have two Lua functions, getSongLyrics and getSongTitle, whose outputs are displayed in a conky window.
getSongLyrics uses a python script that runs sptlrx pipe and outputs it into a FIFO file, which ...
0
votes
2
answers
124
views
New to fifo in linux, reading with python produces gibberish? (binary)
I am trying to grab some sensor data so I can toss it into a influxdb. We have very old sensors writing this out to a server via a fifo on that server. I know I can read it (made a quick program):
# ...
0
votes
1
answer
538
views
Eventbridge Pipe that adds a dynamic MessageGroupID without altering the message body
I have a SQS queue which feeds a FIFO queue using an eventbridge pipe. The pipe grabs a value from the payload and then adds that to the MessageGroupID using a JSONpath expression.
import { SqsTarget }...
1
vote
0
answers
55
views
Redirecting python script's stdin to fifo results in RuntimeError: input(): lost sys.stdin
I have this python script that's meant to function as a server which reads commands from stdin which is redirected to a fifo:
test.py:
while True:
try:
line = input()
except EOFError:
...
-2
votes
1
answer
453
views
How to handle the read latency in Async FIFO?
I am using Xilinx FIFO generator core in my project. I have module, say M1, which assersts fifo_rd_en signal to the fifo that i am using. However, the fifo has a read latency of 2 clock cycles. How ...
2
votes
0
answers
117
views
Implementing a FIFO allocation between two lists in Python
I am trying to write an algorithm in Python to link quantities in a FIFO fashion between two different series (of length N). The input is two lists, 'instructions' and 'responses'.
The two lists ...
0
votes
0
answers
113
views
Data Missing in FIFO stream after DMA transfer
We have a DMA design with FIFO stream input.
We let FIFO accumulate the entirety of data stream i.e., 0x8001 depth and width is 32 bit.
Then we cut off the Input stream to FIFO since it is external.
...