Questions tagged [verilog]
Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.
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Trying to do both synthesis and simulation for iCE40 UP5K when using internal clock and LED driver, but can only get one or the other [closed]
Before putting in an order for an Upduino to take another stab at learning about FPGAs, I figured I'd get the toolchain (yosys and nextpnr) figured out first and work through some tutorials. This was ...
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Different outputs for RTL and gate level netlist simulations for a latch used in clock gating
I am trying to implement clock gating logic manually using a latch and an AND gate as shown in the figure.
The latch has an enable (en) and a done signal which are ...
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What to do when a Verilog state machine simulation doesn't reflect the signals?
I'm working on a Verilog project using ModelSim, and I've created a testbench to simulate the behavior of a module called Elevator_FSM, which models an elevator's operation.
My goal is to assign ...
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1
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Analyzing unexpected output from Verilog bit unpacking and reassembly logic
I'm working on a Verilog task that rearranges bits from a 312-bit word into a new 312-bit format using 8-bit temporary storage (temp[39]). Below is a simplified ...
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How blocking assignment affect non-blocking assignment in Verilog?
module t;
reg a;
initial a <= #4 0;
initial a <= #4 1;
initial $monitor ($time,,"a = %b", a);
endmodule
Output of above Verilog code is:
...
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0
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Interfacing ADS1115 ADC with Microchip PolarFire SoC Discovery Kit
I have been trying to connect the ADS1115 ADC with my Microchip PolarFire SoC discovery kit FPGA board, I have written the FSM for I2C master by collecting the code from various sources because I am ...
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Why is Vivado connecting this reset to the CE pin when the R pin is available?
Vivado is connecting up the reset signal through a LUT to the CE pin of the FDRE, even though the R pin is available. This is a 2k signal, and it's using up 2k LUTs to do this, unnecessarily. Any ...
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1
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Is my Finite State Machine Moore or Mealy?
Can someone please tell me whether the following FSM that I designed is Moore or Mealy? It is a UART Transmitter.
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Must a `for` loop be within an `initial,always` block?
I got two errors when using Vivado.
module top;
reg i_clk;
always
begin
for (u=0;u<3;u=u+1){$display(" %d ",i_clk)}
end
<...
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1
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How to calculate bits number needs to store `1.111` in verilog HDL?
The function $clog2 returns the ceiling of log2 of the given argument.
This is typically used to calculate the minimum width required to
address a memory of given size.
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What causes the same schematic when Verilog has an "assign" statement or not?
Reproduce the problem by 2 Verilog HDL code examples.
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Dot product of 2 arrays in Verilog (MIPS32 Processor)
I am trying to write a testbench in Verilog for computing dot product of two arrays.
The base code for which the testbench has to be written is:
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SystemVerilog's $fdisplay/$fopen don't create a file
I am trying to save the results of simulation to a file from a testbench. Here is the problematic snippet:
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