Questions tagged [verilog]
Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.
2,055 questions
- Bountied 0
- Unanswered
- Frequent
- Score
- Trending
- Week
- Month
- Unanswered (my tags)
1
vote
1
answer
48
views
Why is the waveform not matching? (2 clock delay in FSM code)
Context : I have been tasked with testing a HC-04 Ultrasonic sensor with Verilog, and below is the Verilog code, the testbench and the waveform that I am getting,
...
-1
votes
0
answers
49
views
Changing initial value of register causes incrementor to jump
I am learning to use block memory in Quartus, and am seeing something very strange in my test bench results. My simple verilog code is below, and the test bench just lets it run for a few thousand ...
1
vote
0
answers
48
views
Trying to do both synthesis and simulation for iCE40 UP5K when using internal clock and LED driver, but can only get one or the other [closed]
Before putting in an order for an Upduino to take another stab at learning about FPGAs, I figured I'd get the toolchain (yosys and nextpnr) figured out first and work through some tutorials. This was ...
1
vote
1
answer
85
views
Different outputs for RTL and gate level netlist simulations for a latch used in clock gating
I am trying to implement clock gating logic manually using a latch and an AND gate as shown in the figure.
The latch has an enable (en) and a done signal which are ...
2
votes
1
answer
67
views
1
vote
1
answer
80
views
What to do when a Verilog state machine simulation doesn't reflect the signals?
I'm working on a Verilog project using ModelSim, and I've created a testbench to simulate the behavior of a module called Elevator_FSM, which models an elevator's operation.
My goal is to assign ...
2
votes
1
answer
116
views
Analyzing unexpected output from Verilog bit unpacking and reassembly logic
I'm working on a Verilog task that rearranges bits from a 312-bit word into a new 312-bit format using 8-bit temporary storage (temp[39]). Below is a simplified ...
-1
votes
1
answer
74
views
1
vote
1
answer
64
views
How blocking assignment affect non-blocking assignment in Verilog?
module t;
reg a;
initial a <= #4 0;
initial a <= #4 1;
initial $monitor ($time,,"a = %b", a);
endmodule
Output of above Verilog code is:
...
1
vote
0
answers
71
views
Interfacing ADS1115 ADC with Microchip PolarFire SoC Discovery Kit
I have been trying to connect the ADS1115 ADC with my Microchip PolarFire SoC discovery kit FPGA board, I have written the FSM for I2C master by collecting the code from various sources because I am ...
3
votes
2
answers
426
views
Why is Vivado connecting this reset to the CE pin when the R pin is available?
Vivado is connecting up the reset signal through a LUT to the CE pin of the FDRE, even though the R pin is available. This is a 2k signal, and it's using up 2k LUTs to do this, unnecessarily. Any ...
0
votes
1
answer
167
views
Is my Finite State Machine Moore or Mealy?
Can someone please tell me whether the following FSM that I designed is Moore or Mealy? It is a UART Transmitter.
...
-3
votes
1
answer
144
views
Must a `for` loop be within an `initial,always` block?
I got two errors when using Vivado.
module top;
reg i_clk;
always
begin
for (u=0;u<3;u=u+1){$display(" %d ",i_clk)}
end
<...
0
votes
1
answer
123
views
How to calculate bits number needs to store `1.111` in verilog HDL?
The function $clog2 returns the ceiling of log2 of the given argument.
This is typically used to calculate the minimum width required to
address a memory of given size.
...
3
votes
2
answers
242
views
What causes the same schematic when Verilog has an "assign" statement or not?
Reproduce the problem by 2 Verilog HDL code examples.
...