How blocking assignment affect non-blocking assignment in Verilog?

Question

module t;
reg a;
initial a <= #4 0;
initial a <= #4 1;
initial $monitor ($time,,"a = %b", a);
endmodule

Output of above Verilog code is:

 0 a = x
 4 a = 1

When I added initial a = 1;, more changes happened, but $monitor outputs less:

module t;
reg a;
initial a = 1;
initial a <= #4 0;
initial a <= #4 1;
initial $monitor ($time, ,"a = %b", a);
endmodule

Output of above Verilog code is:

 0 a = x
 

How blocking assignment initial a = 1 affect non-blocking assignment in Verilog?

• kittygirl: Is $monitor a non blocking assignment update event?

Answer 1

Refer to IEEE Std 1800-2023, section 21.2.3 Continuous monitoring:

When a $monitor task is invoked with one or more arguments, the simulator sets up a mechanism whereby each time a variable or an expression in the argument list changes value—with the exception of the $time, $stime, or $realtime system functions—the entire argument list is displayed at the end of the time step as if reported by the $display task.

In your second code example, a only changes value once. At time=0, it changes from x to 1 in this line:

initial a = 1;

This is what is displayed by your simulator.

The other 2 assignments:

initial a <= #4 0;
initial a <= #4 1;

assign a to 0 then back to 1 at time=4. However, there is no net change to a, so $monitor has no change in value to display.

---

You should avoid making multiple assignments to the same signal at the same time to avoid such behavior as this. Your code does not follow standard good Verilog coding practices.

Note: when I run the 2nd code example on 3 different simulators, I get this result:

0 a = 1

Since you get a different result, this is likely a simulation race condition, which is yet another reason not to write code like this.