How do I visualize Verilog/HDL simulation?

Question

I know that execution is a misnomer here, still using it due to lack of a better word. Edit: simulation.

Coming from a programming background, where we have debuggers to step over, in and out of a particular code block and we have watches to monitor the real time values of variables.

Do we have any similar possibilities in the HDL world? This is needed to monitor real time values of reg type variables, procedural block execution and how blocking and non-blocking assignment will work in real time.

Could not find similar functionality in Vivado. Do we have to do the debugging using waveform only?

• Syed: HDL world is not very different from the programming world. L stands for language. For starters, look at this post.
• Elliot Alderson: Does this answer your question? Looking for a program that can simulate a Verilog HDL file
• lousycoder: @ElliotAlderson Unfortunately, it doesn't. I know about HDL simulation software, but I'm keen about the features from the programming language paradigm.
• Elliot Alderson: Perhaps your difficulty stems from the fact that you call it a "programming language", It is better understood if you accept that it is a Hardware Description Language. For those of us who use Verilog, the idea of "monitor real time values" makes no sense because the values are changing on a nanosecond scale. Simulation is the only way to understand how the language works.
• Mitu Raj: If FPGA, on-chip debugging is also possible apart from simulation. What's actually inside the registers and so on...

Answer 1

Look at the Vivado Design Suite Tutorial section on "Stepping Through Source Code". Almost any compiler that simulates Verilog natively (i.e. not translating it to another language like C/C++ first) should have this capability. You should be able to set breakpoints and view the current values of signals at that exact point in time.

• lousycoder: Awesome! Is this feature available only in Vivado 2019 and above? I have a previous version.
• dave_59: 2018.3 has the same section in their docs
• lousycoder: I have found the feature in the Vivado, Thank You!

Answer 2

It's a digital logic circuit so you don't have a notion of execution. The circuit does change state, asynchronously and/or synchronously depending on its design.

Use simulation to prove your design before you try it in a target device. When developing for ASIC, you only have simulation because you can't try it without making the chip.

Writing a decent testbench that exercises your HDL design (not program) and checks its outputs, or lets you examine them, should be an integral part of the design process.

When you then run the simulation, you can see every single logic node you have named (signals and variables in VHDL) on a wave window. This is like a super version of a software debugger - everything is observable.