What changed output display sequence of verilog `initial begin end`?

Question

module n;
reg [3:0] a,b;
integer i;
initial begin
 $monitor("monitor a:%h b:%h @ %0t", a, b, $time);
 for(i=0; i<4; i=i+1) begin
 $strobe("strobe a:%h b:%h @ %0t", a, b, $time);
 $display("display a:%h b:%h @ %0t", a, b, $time);
 case(i)
 0 : a = 4;
 1 : b = 1;
 2 : begin end // do nothing
 3 : {a,b} = 9;
 endcase
 $display("display a:%b b:%b @ %0t", a, b, $time);
 #1;//after delete this line,output changed
 end
end
endmodule

Output of above verilog script is:

display a:x b:x @ 0
display a:0100 b:xxxx @ 0
monitor a:4 b:x @ 0
strobe a:4 b:x @ 0
display a:4 b:x @ 1000
display a:0100 b:0001 @ 1000
strobe a:4 b:1 @ 1000
monitor a:4 b:1 @ 1000
display a:4 b:1 @ 2000
display a:0100 b:0001 @ 2000
strobe a:4 b:1 @ 2000
display a:4 b:1 @ 3000
display a:0000 b:1001 @ 3000
strobe a:0 b:9 @ 3000
monitor a:0 b:9 @ 3000

When I delete #1,the output changed:

display a:x b:x @ 0
display a:0100 b:xxxx @ 0
display a:4 b:x @ 0
display a:0100 b:0001 @ 0
display a:4 b:1 @ 0
display a:0100 b:0001 @ 0
display a:4 b:1 @ 0
display a:0000 b:1001 @ 0
monitor a:0 b:9 @ 0
strobe a:0 b:9 @ 0
strobe a:0 b:9 @ 0
strobe a:0 b:9 @ 0
strobe a:0 b:9 @ 0

And the $time become 0.
What changed output display sequence?

Answer 1

With the delay, the loop takes multiple time steps to complete as the delay is used in a blocking fashion. Each time step will thus have a monitor print if anything has changed and a strobe print.

Without the delay, all passes through the loop occur at time 0 because all of the statements take zero time to execute.

As they are all the same time step, all of the monitor and strobe statements are shown together at the end because they are executed at the end of the current time step.

• kittygirl: Statements are wrapped using begin and end keywords and will be executed sequentially in the given order, one after the other.Then,I assume $strobe and $display will execute as the order.In the second output,does $strobe and $display broke the order?
• dave_59: You assumed incorrectly as you’ve been told many times
• kittygirl: @dave_59 Pls let us know if any content in the verilog manual about $strobe broke begin-end sequence
• dave_59: Read section 21.2.2 Strobed monitoring
• Tom Carpenter: @kittygirl will be executed sequentially in the given order is an introductory simplification to give a rough idea of how the language works. In reality as with all simplifications it's not always strictly true.