how to show the internal wire wave in verilog output?

Question

Suppose I have a code written as

module ruff(q,qbar,cp,s,r,clear); 
//port declaration from the I/O diagram 
output q,qbar; 
input s,r,clear,cp; 
// Instantiate S_R_FF 
//s_r_ff sr(q,qbar,cp,s,r,clear); 
wire clkbar,sin,rin; 
assign clkbar=~cp, 
 sin=(s&clear&clkbar), 
 rin=(r&clear&clkbar); 
assign q=~(rin|qbar), 
 qbar=~(sin | q); 
endmodule 

What is a way to show clkbar,sin,rin( wire clkbar,sin,rin;) waveform also in output window in Xillnx?

Answer 1

One of the simulator windows shows a hierarchical view of your project. Use that window to navigate to the particular instance of the module that you're interested in. Another window shows the signals that are visible at that level of the hierarchy. Right-click on the signal(s) you want to see and select "add to wave".

(I believe this advice works for both the Modelsim simulator and the built-in ISE simulator.)