BCD adder not seeing output of 9's complementer in verilog

Question

I am attempting to construct a BCD adder-subtractor circuit in verilog using a BCD adder circuit and BCD-to-9's complement circuit.

The modules operate correctly individually. However, when instantiated as part of BCD adder-subtractor circuit, I do not get the correct output sum from the BCD adder when simulated.

Instead, I get only the LSB of the complementer going to the BCD Adder and the following warning, which somewhat implies this is what is happening: "[PCDPC]- Port size (4) does not match connection size (1) for port 'N'" and "PCDPC] - Port size (4) does not match connection size (1) for port 'B'". N being the output of the 9's complementer and B being the Addend of the BCD adder.

This is somewhat frustrating, as the port size for N and B are correctly defined in their relevant modules.

The module declaration are as follows:

module BCDto9Compl(A, N);
input [3:0] A;
output [3:0] N;
module BCD_Adder(A, B, Cin, S, Cout);
input [3:0] A;
input [3:0] B;
BCD_AdderSub(A, B, Cin, S, Cout);
input [3:0] A;
input [3:0] B;

and module instantiation is as follows:

instantiate modules

BCDto9Compl B9C(B, F);
BCD_Adder BcA(A, F, Cin, S, Cout);

I would very much appreciate any insight that you may be able to give.

Thanks

• Tom Carpenter: We cannot help you from the code you have shown - you need to post a "minimal, complete, and verifiable example". My guess is that you haven't declared "F" in your instantiation, so it is defaulting to a 1-bit wire.
• aLoHa: Tom, your guess was spot on. You've saved me from a lot of headache. Thanks for your help. It is very much appreciated. I will also try to provide a complete example in the future when posing a question .
• Oldfart: To prevent errors like that you should use the new style port definitions. module B9C ( input [3:0] B,.. Also when instancing a module use reference by-name: `BcA( .A(A), .F(F)...
• Matt: And you should never use position based port assignments. Always use name based connection.
• aLoHa: Thank you all for your comments, which is very much appreciated. It is true that I have been creating the majority of my modules based on the old-style port assignment. However, the general consensus seems to be that the new style name based port assignment and instantiating modules using reference by name are the way forward, so I will heed your advice.

Answer 1

My guess is that you haven't declared F in your instantiation, and as such the synthesis tool is implicitly creating it. Implicit nets can either end up the correct size, or default to a 1-bit wire depending on the synthesis tool.

You should always create all wires and registers explicitly. Additionally using explicit (name-based) port assignments rather than implicit (position-based) is a preferred method to avoid potential issues if you change something down the line.

BCDto9Compl B9C(B, F);

Becomes:

wire [3:0] B;
wire [3:0] F;
BCDto9Compl B9C(.A(B), .N(F));

I would also try to use more descriptive naming for nets and registers where possible.