Must a `for` loop be within an `initial,always` block?

Question

I got two errors when using Vivado.

module top; 
 reg i_clk;
 always
 begin
 for (u=0;u<3;u=u+1){$display(" %d ",i_clk)}
 end

ERRROR: syntax error near ';'

And:

module top; 
 reg i_clk;
 integer u;
 begin
 for (u=0;u<3;u=u+1)
 $display(" %d ",i_clk);
 end

ERROR:u is not instant.

I am learning Verilog 2005 standard. I have no idea how to fix these two errors.

Must a for loop be within an initial,always block?

Answer 1

You're getting your syntax wong. Verilog is not C - it doesn't use {} for blocks, it uses begin-end.

So your first code should be:

always begin
 for (u=0;u<3;u=u+1) begin
 $display(" %d ",i_clk)
 end
end

Although I don't know what you are hoping to achieve. The code will immediately print the value of i_clk constantly, most likely causing the simulator to lock up - always begin just runs constantly with no trigger. The for loop also executes in zero time.

---

A for loop must be inside either a procedural block (initial/begin), a task or function, or a generate block. So the second example is again not a valid syntax.

• kittygirl: Does begin end can be omitted when there's only one sentence?
• Tom Carpenter: @kittygirl It can be, but I prefer to always include them as it makes it easier to maintain the code.