Syntax error near variable and range in VHDL

Question

I learnt Java last year and started to learn VHDL and implementation on BASYS3 this year. I am just trying to display numbers on the seven segment starting from 0 and each time a push button is pushed the number will increase. I am familiar with the input and output declarations but I was not able to declare my integer variable as follows in VHDL vivado;

architecture Behavioral of top_module is
begin
shared variable total_foul : integer range 0 to 5;
total_foul := 0;

It keeps saying that there is a syntax error near variable and range which I couldn't find out. Also I tried to write the code for seven segment in case statements as follows;

 begin
 case total_foul is 
 when 1 => LED <= "1001111"; -- "1" 
 when 2 => LED <= "0010010"; -- "2" 
 when 3 => LED <= "0000110"; -- "3" 
 when 4 => LED <= "1001100"; -- "4" 
 when 5 => LED <= "0100100"; -- "5" 
 when others => LED <= "0000001"; -- "0" 

But this also states that there is a syntax error near when.

The overall code for now is;

entity top_module is
 Port ( increase : in STD_LOGIC;
 decrease : in STD_LOGIC;
 foul : in STD_LOGIC;
 anode : out STD_LOGIC_VECTOR (3 downto 0);
 LED : out STD_LOGIC_VECTOR (6 downto 0));
end top_module;
architecture Behavioral of top_module is
begin
anode <= "1111";
shared variable total_foul : integer range 0 to 5;
total_foul := 0;
begin
if foul = '1' then
 if increase = '1' and decrease = '0' then
 total_foul := total_foul + 1;
 elsif decrease = '1' and increase = '0' then
 total_foul := total_foul - 1;
 end if;
 begin
 case total_foul is 
 when 1 => LED <= "1001111"; -- "1" 
 when 2 => LED <= "0010010"; -- "2" 
 when 3 => LED <= "0000110"; -- "3" 
 when 4 => LED <= "1001100"; -- "4" 
 when 5 => LED <= "0100100"; -- "5" 
 when others => LED <= "0000001"; -- "0" 
end Behavioral;

Thanks for everyone in advance.

• Marcus Müller: make sure you're using VHDL93. Before, you couldn't declare shared variables in architectures. Also, the verbatim error text would possibly be helpful.
• Ron Beyer: Aren't you supposed to have an end case; at the bottom of the case set? You also seem to be missing an end if; for the if foul = '1' then set. I'd also suggest indenting correctly (the case when's should be indented from the case)
• Dave Tweed: There are too many begins and not enough ends. You really need to take another look at the basic syntax of the statements you're using.
• user16324: Looks like you have no digital hardware design experience. Avoid shared variables for a start, learn signals instead. Useful search terms : clocked process, signal assignment semantics, delta cycles. And stackoverflow.com/questions/13954193/…
• Mitu Raj: Shared variable is not a good design choice. And never code VHDL like C/C++/JAVA etc. It is very different as its a HDL not software language. You should start VHDL from basics

Answer 1

Stripping out the parts of your code that are not problematic, we have:

architecture Behavioral of top_module is
begin
 shared variable total_foul : integer range 0 to 5;
 begin
 if foul = '1' then
 begin
 case total_foul is 
 when 1 => LED <= "1001111"; -- "1" 
 when 2 => LED <= "0010010"; -- "2" 
 when 3 => LED <= "0000110"; -- "3" 
 when 4 => LED <= "1001100"; -- "4" 
 when 5 => LED <= "0100100"; -- "5" 
 when others => LED <= "0000001"; -- "0" 
end Behavioral;

The first issue is your shared variable. These can only be declared in a declarative region, in this case, it looks like you wanted it in the architecture declarative region, which is before the first begin in the code above.

The next problem is your second begin statement. What was this supposed to do? It looks more like you wanted to start a process here.

There is a 3rd begin after the if foul = '1' line. Again, what is this meant to do? It does not match any valid code pattern, so I suggest you just get rid of it.

Your case statement starts off OK, but where is the matching end case;?

Going back to the if foul = '1' line, it has no matching end if;.

---

You need to go back and look at some examples of simple VHDL architectures, then carefully write code with these in mind. Per a comment, you should also avoid using a shared variable until you really understand why you are using this, and not a signal or variable.