What causes the same schematic when Verilog has an "assign" statement or not?

Question

Reproduce the problem by 2 Verilog HDL code examples.

`timescale 1ns / 1ps
module shift_reg (clock, reset, shiftreg);
input clock;
input reset;
output [4:0] shiftreg;
reg [4:0] shiftreg;
always @ (posedge clock)
begin
 if (reset)
 shiftreg = shiftreg >> 1;
 else 
 shiftreg = shiftreg << 1;
 end
//assign shiftreg2=shiftreg;
endmodule

The second:

`timescale 1ns / 1ps
module shift_reg (clock, reset, shiftreg2);
input clock;
input reset;
output [4:0] shiftreg2;
reg [4:0] shiftreg;
always @ (posedge clock)
begin
 if (reset)
 shiftreg = shiftreg >> 1;
 else 
 shiftreg = shiftreg << 1;
 end
assign shiftreg2=shiftreg;
endmodule

These 2 codes get the same schematic:

enter image description here

As to example 1, there's no assign port=reg, output shiftreg should has no any connection. What makes Vivado output the same schematic?

Answer 1

As to example 1, there's no assign port=reg, output shiftreg should has no any connection.

You have in your first example the declarations output [4:0] shiftreg; and reg [4:0] shiftreg;. These two definitions have the same name, and are thus treated as the same entity. You don't need the separate assign statement because they are already the same signal.

In the second example you have output [4:0] shiftreg2; and reg [4:0] shiftreg;. These have different names, so are not the same signal. You therefore need the assign shiftreg2 = shiftreg; if you want the output to be driven to the same value as the internal signal.

The RTL view is a general interpretation of what the code describes. Any names shown in the schematic are entirely at the mercy of the synthesizers optimisation, and may not directly represent names in the code. If you have to signals with different names but driven by the same logic, the duplicate name is frequently omitted.

---

As a side note, this is one of the reasons why Verilog 2001 introduced a new way of declaring ports to avoid this confusion and duplication:

module shift_reg (
 input clock,
 input reset,
 output reg [4:0] shiftreg
);

Unless you have a compelling reason not to (e.g. very old tools with no support), then I would suggest getting used to the new (well 24 years old now!) style of port lists as they are much easier to maintain.

• Michael: In addition to the port declaration: I would also suggest using System Verilog with the logic type to avoid the whole confusion with reg and wire.

Answer 2

There is no functional difference between your 2 specific Verilog code examples. It is no surprise that Vivado produces similar schematics (aside from the shiftreg2 output name). The output name does not affect the result.

There are many different ways to write Verilog code to achieve the same schematic or synthesized result. It is often a matter of coding style. The first code example is simpler because it does not have the redundant assign.

• kittygirl: As to script 1,There's no assign port=reg.You will get different result when you change output name from shiftreg to shiftreg2.Does output name affect result?
• kittygirl: ,It's not OK to guess the output of vivado black box.How could vivado connect output port without assign?I reviewed verilog 2005 standard,cannot find answer.