When I assign a signal with x in verilog, what happend in circuit?

Question

I want to know what happen in circuit if I assign wire_a = 2'bx1.

Actually I used a module MuxKeyWithDefault, I want to use a key with signal x, so I write down my code as follows:

MuxKeyWithDefault #(2, 17, 32) mux_dnpc (npc,{fun7,fun3,op_code}, snpc,{
 17'bxxxxxxxxxx1101111, pc + imm, 
 17'bxxxxxxx0001100111, (src1_data + imm)&~1
 });

This code can compair {fun7,fun3,op_code} with key 17'bxxxxxxxxxx1101111 and 17'bxxxxxxx0001100111. If key is hitted in key_list, npc will be assgin by values as follows.

But I fund that the first key in key_list only can be paird when x=0. In other words, 17'b11111111111101111 cannot be hitted in key_list.

So I write down the signal test, and I have simulated it in verilator and I found that x comes to 0 in wave.

I want to know why and is it possible to assign a signal with uncertain value like x ?

And this is the minimal example that you can run by yourself to observe the signal :

module EXU(
 input clk,
 input rst,
 input [31:0]inst,
 output [31:0] pc
 );
 
 wire [6:0] op_code = inst[6:0];
 wire [2:0] fun3 = inst[14:12];
 wire [6:0] fun7 = inst[31:25];
 MuxKeyWithDefault #(2, 17, 32) mux_dnpc (pc,{fun7,fun3,op_code}, 32'b0,{
 17'bxxxxxxxxxx1101111, 32'b1, 
 17'bxxxxxxx0001100111, 32'd2,
 });
endmodule
module MuxKeyWithDefault #(NR_KEY = 2, KEY_LEN = 1, DATA_LEN = 1) (
 output [DATA_LEN-1:0] out,
 input [KEY_LEN-1:0] key,
 input [DATA_LEN-1:0] default_out,
 input [NR_KEY*(KEY_LEN + DATA_LEN)-1:0] lut
);
 MuxKeyInternal #(NR_KEY, KEY_LEN, DATA_LEN, 1) i0 (out, key, default_out, lut);
endmodule
module MuxKeyInternal #(NR_KEY = 2, KEY_LEN = 1, DATA_LEN = 1, HAS_DEFAULT = 0) (
 output reg [DATA_LEN-1:0] out,
 input [KEY_LEN-1:0] key,
 input [DATA_LEN-1:0] default_out,
 input [NR_KEY*(KEY_LEN + DATA_LEN)-1:0] lut
);
 localparam PAIR_LEN = KEY_LEN + DATA_LEN;
 wire [PAIR_LEN-1:0] pair_list [NR_KEY-1:0];
 wire [KEY_LEN-1:0] key_list [NR_KEY-1:0];
 wire [DATA_LEN-1:0] data_list [NR_KEY-1:0];
 genvar n;
 generate
 for (n = 0; n < NR_KEY; n = n + 1) begin
 assign pair_list[n] = lut[PAIR_LEN*(n+1)-1 : PAIR_LEN*n];
 assign data_list[n] = pair_list[n][DATA_LEN-1:0];
 assign key_list[n] = pair_list[n][PAIR_LEN-1:DATA_LEN];
 end
 endgenerate
 reg [DATA_LEN-1 : 0] lut_out;
 reg hit;
 integer i;
 always @(*) begin
 lut_out = 0;
 hit = 0;
 for (i = 0; i < NR_KEY; i = i + 1) begin
 lut_out = lut_out | ({DATA_LEN{key == key_list[i]}} & data_list[i]);
 hit = hit | (key == key_list[i]);
 end
 if (!HAS_DEFAULT) out = lut_out;
 else out = (hit ? lut_out : default_out);
 end
endmodule

This is the c code:

#include "verilated.h"
#include "verilated_vcd_c.h"
#include "VEXU.h"
#include <unistd.h>
#include <stdio.h>
VerilatedContext *contextp = NULL;
VerilatedVcdC *tfp = NULL;
VEXU *top;
using namespace std;
void step_and_dump_wave()
{
 contextp->timeInc(1);
 tfp->dump(contextp->time());
}
void sim_init()
{
 contextp = new VerilatedContext;
 tfp = new VerilatedVcdC;
 top = new VEXU;
 contextp->traceEverOn(true);
 top->trace(tfp, 0);
 tfp->open("dump.vcd");
}
void sim_exit()
{
 step_and_dump_wave();
 tfp->close();
}
void single_cycle()
{
 top->clk = 0;
 top->eval();
 step_and_dump_wave();
 top->clk = 1;
 top->eval();
 step_and_dump_wave();
}
void reset(int n)
{
 top->rst = 1;
 while (n-- > 0)
 single_cycle();
 top->rst = 0;
}
int main(int argc, char *argv[])
{
 sim_init();
 reset(10);
 top->inst = 0x00C000EF;
 single_cycle();
 top->inst = 0xFE9FF0EF;
 single_cycle();
 sim_exit();
 top->final();
}

This is Makefile

all:
 -@mkdir ./build/
 verilator -MMD --build -cc -O3 --x-assign fast --x-initial fast --assert --trace --coverage \
 --top-module EXU EXU.v MuxKeyInternal.v MuxKeyWithDefault.v\
 -CFLAGS -DTOP_NAME=EXU -CFLAGS -I/usr/include \
 --Mdir ./build/obj_dir --exe ../main.cpp -o ../EXU
 ./build/EXU
clean:
 @rm -rf ./buil

You can run this example, and you'll see the wave like this: enter image description here

I want to make key 1FFEF can hit key_list[1], what should I do?

• Chester Gillon: Does the answer in What exactly do x and z values represent in Verilog? help?
• Daria: @ChesterGillon I had read the link you posed, but I actually didn't understand how to use uncertin value in my case.
• Daria: @toolic thanks for your advice , I had add my code.
• Daria: @toolic I had post part of my verilator code, but I cann't post my full verilatro code because it's to long.
• Daria: @toolic Great thanks for you. I had post a minal example which I have tested in my computer.

Answer 1

I checked Verilator's docs and I knew that x will be replaced by 1 or 0 depending on option --x-assign. So I should'nt assgin a x to a signal in my situation. And then I mapped these parameters to unique values instead of values with x.

Thanks for everyone who helped me agian.