Verilog assign result of module

Question

I am trying to take the result of a module and assign it to an input of another module, however I keep getting an error about declaring net types. I feel like I'm missing part of the syntax rules here, but I've been unable to find a solution. Any help much appreciated!

Some nonsense code to demonstrate:

module m1(SW, LED);
 input SW;
 output LED;
 reg [3:0] out;
 reg [1:0] x;
 assign x = out[1:0];
 moduleA mA(.in(SW), .out(out));
 moduleA mB(.in(x), .out(LED));

Answer 1

As the other answers say, your problem is declaring x and out as register type.

When you assign to something in an assign statement, or by connecting it to an output port of a module instance, you need to declare it as a wire instead of a reg.

I'd also add that your out variable is redundant. You can use one variable to connect to the output of one module and the input of the other:

 wire [1:0] x;
 moduleA mA(.in(SW), .out(x));
 moduleA mB(.in(x), .out(LED));

Saves you declaring and keeping track of an extra variable and an extra assign statement.

Answer 2

You can't assign to a register using the assign keyword

You can however assign to a wire.

wire [1:0] x;
assign x = out[1:0];

But it is possible to asynchronously assign within an always block (i.e. without a clock) to a register:

reg [1:0] x;
always @ * begin
 x <= out[1:0];
end

---

Two simple rules about net types:

• wire = assign
• reg = always (and/or initial)

Answer 3

The crucial point you're missing is the difference between net types and variable types.

net is a connection wire, usually this is keyword wire but there are other net types for tristate, wired-or, wire-and, and a few other exotic cases. You use net types for structural description.

variable is "temporary storage of programming data", usually this is keyword reg but could also be integer or real in a test bench. Often reg ends up being synthesized with a D-flip-flop register, but not always.

A useful resource is Sutherland HDL's Verilog HDL Quick Reference Guide