How can one test that a signal is High-Z when simulating with Verilator?

Question

Say I have this module:

module Test(
 input logic a,
 output logic b
);
 assign output = a ? 1'bZ : 1'b1;
endmodule;

Currently, when testing the module with a C++ testbench, the output of the simulation shows the High-Z state as 0 (I assume because Verilator models logic lines as integers).

Is there any capability to test whether a 0 is a numerical 0 or a High-Z?

• Rajesh Shashi Kumar: Is case equality (===) something that can help with your problem?
• Rainb: I think verilator does not support X or Z

Answer 1

I don't think so. I believe you can write the expression b === 'bz within your SystemVerilog code, and that returns true (1'b1) within your code when b should have had a z state, but the actual output gets converted to a 0.