Unable to open input file in Verilog

Question

I'm having trouble running my Verilog code.

Here is my code:

module hello(A,B);
input A;
output B;
assign B = A; 
endmodule

And here is my testbench:

`timescale 1ns / 1ns
`include "hello.v"
 
module hello_tb;
reg A;
wire B;
hello uut(A, B);
initial begin 
 $dumfile("hello_tb.vcd");
 $dumpvar(0, hello_tb);
 A = 20;
 #20;
 A = -1;
 #20;
 A = 0;
 #20;
 $display("Test complete");
end
endmodule

These are the commands I'm running on my terminal:

iverilog -o hello_tb.vvp hello_tb.v

vvp hello_tb.vvp

And that's the error I'm getting:

hello_tb.vvp: Unable to open input file.

I don't know what I am doing wrong.

Answer 1

You have syntax errors in your testbench file.

I get different error messages from you, but it is likely that I am running a different version of iverilog. It's too bad you don't get a more specific error message. Here are the errors I get:

iverilog -o hello_tb.vvp hello_tb.v
vvp hello_tb.vvp
hello_tb.v:13: Error: System task/function $dumfile() is not defined by any module.
hello_tb.v:14: Error: System task/function $dumpvar() is not defined by any module.
hello_tb.vvp: Program not runnable, 2 errors.

To fix those errors, change the testbench lines to:

$dumpfile("hello_tb.vcd");
$dumpvars(0, hello_tb);

That works for me.

It is important to note that both of the Verilog source code files (hello_tb.v and hello.v) are in the current directory when I run the iverilog command.

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It is also unusual to assign values like 20 and -1 to a 1-bit signal (A) in the testbench.