How to resolve the error unable to open input file in Verilog?

Question

I was asked to implement a 16-to-1 multiplexer using a 4-to-1 multiplexer using the conditional statement. Writing the Verilog code and the testbench code wasn't a big issue however I'm unable to understand what I can do to resolve the error unable to open input file. See the Verilog and testbench code below.

The simulator used for obtaining the waveforms is GTKWave. The Verilog code and testbench code are saved in C:\iverilog\bin\MultiplexersLab

Here is the Verilog code (file name: mux16to1.v):

module mux16to1(w,s,f);
input [15:0] w;
input [3:0] s;
output f;
wire [3:0]x;
mux4to1 m1(w[3:0],s[1:0],x[0]);
mux4to1 m2(w[7:4],s[1:0],x[1]);
mux4to1 m3(w[11:8],s[1:0],x[2]);
mux4to1 m4(w[15:12],s[1:0],x[3]);
mux4to1 m5(x,s[1:0],f);
endmodule 
module mux4to1(w,s,f);
input [3:0]w;
input [1:0]s;
output f;
reg f;
always @(w or s)
f = s[1]?(s[0]?w[3]:w[2]):(s[0]?w[1]:w[0]);
endmodule

Testbench code (file name: exercise2_tb.v):

`timescale 1ns/1ns
`include "mux16to1.v"
module exercise2_tb();
reg[15:0] w;
reg[3:0] s;
wire f;
mux16to1 test(w,s,f);
initial 
begin
 $dumpfile("exercise2.vcd");
 $dumpvars(0,exercise2_tb);
 w = 16'b0000000000000001; s = 4'b0000;#20;
 w = 16'b1000000000000000; s = 4'b1111;#20;
 w = 16'b0000000000000010; s = 4'b0010;#20;
 w = 16'b0000010000000000; s = 4'b0101;#20;
 $display("Test Complete");
end
endmodule

Output Generated:

PS C:\iverilog\bin\MultiplexersLab> iverilog -o exericse2_tb.vvp exercise2_tb.v
PS C:\iverilog\bin\MultiplexersLab> vvp exercise2_tb.vvp
exercise2_tb.vvp: Unable to open input file.

Answer 1

The vvp command tells you that the file named exercise2_tb.vvp does not exist. It does not exist because you specified an output file named exericse2_tb.vvp on the iverilog command line (different spelling: exercise2 vs. exericse2).

To run vvp on the file you created, change:

vvp exercise2_tb.vvp

to:

vvp exericse2_tb.vvp

With that change, I see the following output:

VCD info: dumpfile exercise2.vcd opened for output.
Test Complete

---

Or, change the iverilog command to:

iverilog -o exercise2_tb.vvp exercise2_tb.v