Why do I get a compile error when I connect output reg of one module to input of another?

Question

My intention is to connect the output reg 'state' from the 'moore' module to the input of the 'combinational' module (reg 'state' in this case is meant to act as a flip flop).

module lab3(input [9:0] SW, input [3:0] KEY,
 output [6:0] HEX0, output [6:0] HEX1, output [6:0] HEX2,
 output [6:0] HEX3, output [6:0] HEX4, output [6:0] HEX5,
 output [9:0] LEDR);
wire clk = ~KEY[0]; // this is your clock
wire rst_n = KEY[3]; // this is your reset; your reset should be synchronous and active-low
wire [3:0] state_in;
reg [3:0] b;
assign state_in = state;
 // moore component
 module moore(input [3:0] SW, 
 input clk, 
 input rst_n, 
 output reg [3:0] state);
 endmodule: moore
 // combinational component
 module combinational(input [3:0] SW, input [3:0] state_in,
 output [6:0] HEX0, output [6:0] HEX1, output [6:0] HEX2,
 output [6:0] HEX3, output [6:0] HEX4, output [6:0] HEX5);
 endmodule: combinational
 endmodule: lab3

I know that a reg can drive a wire using an 'assign' statement, which is what I tried above. The file compiles when the placeholder reg 'b' is used to drive the wire, but when I try to connect it to the output reg 'state' from the 'moore' module, it doesn't compile. I'm struggling to understand why this is the case since I'm new to Verilog.

Answer 1

I don't see where state is defined in module lab3... so the statement assign state_in = state; has the effect of implicitly declaring a 1-bit wire called state inside module lab3. This is in no way related to the similarly named output port of module moore, because it's in a different lexical scope.

To connect ports from one instance of a module to another instance of a module, you have to create the instances at a higher level.

Inside the scope of module lab3, you need to create an instance of moore and an instance of combinational, and for best practice declare the connecting wires too (otherwise they default to a single 1-bit width). That's where you connect the input ports and output ports of the various instances together. Not inside the definition of module moore or module combinational.

If you're coming to Verilog from a computer programming language like C++ or Java, it's going to be very confusing, because you may be accustomed to reading the code as a series of steps to be performed by a computer. But in Verilog, it's not like that at all: it's all about defining a single piece of hardware, which exists in its complete and final form for the entire scope of the project. So while it's tempting to think of Verilog modules as if they were C++ class definitions, that's not really a good analogy. It only gets you as far as definition/instance, except that all of the instances must be created at compile time, and there's no dynamic allocation.

Answer 2

The 1st step is to move the moore and combinational module bodies out of the lab3 module.

The 2nd step is to place an instance of the moore and combinational modules inside the lab3 module. Use unique instance names, like i0 and i1.

The 3rd step is to make signal connections to the instances. I use the connection-by-name style in this example:

module lab3(input [9:0] SW, input [3:0] KEY,
 output [6:0] HEX0, output [6:0] HEX1, output [6:0] HEX2,
 output [6:0] HEX3, output [6:0] HEX4, output [6:0] HEX5,
 output [9:0] LEDR);
wire clk = ~KEY[0]; // this is your clock
wire rst_n = KEY[3]; // this is your reset; your reset should be synchronous and active-low
wire [3:0] state_in;
reg [3:0] b;
moore i0 (.state (state_in), .SW(SW[3:0]), .clk(clk), .rst_n(rst_n));
combinational i1 (.state_in (state_in) /* connect other signals here */);
endmodule: lab3
module moore(input [3:0] SW, 
 input clk, 
 input rst_n, 
 output reg [3:0] state);
endmodule: moore
module combinational(input [3:0] SW, input [3:0] state_in,
 output [6:0] HEX0, output [6:0] HEX1, output [6:0] HEX2,
 output [6:0] HEX3, output [6:0] HEX4, output [6:0] HEX5);
endmodule: combinational

The above code compiles without any errors. You need to complete the connections yourself for the i1 instance.

Note that there is no need to use assign for the state; just connect the same signal (state_in) directly to both instances.

See also: How to instantiate a module