Why do I get the a.out 1:syntax error when I run Icarus Verilog simulation?

Question

module round_robbin
 #(
 parameter UNIT = 3,
 parameter CH1_WT = 1,
 parameter CH2_WT = 1,
 parameter CH3_WT = 1,
 parameter CH4_WT = 1,
 parameter ADDR_WIDTH = 8,
 parameter DATA_WIDTH = 8,
 parameter CHANNELS = 4
 )(
 input i_rt_lt,
 input i_clk,
 input i_rst_,
 input [ADDR_WIDTH:1] i_addr [CHANNELS:1],
 input [DATA_WIDTH:1] i_data [CHANNELS:1],
 input [CHANNELS:1] i_wr,
 input [CHANNELS:1] i_rd,
 output reg [ADDR_WIDTH:1] o_addr,
 output reg [DATA_WIDTH:1] o_data,
 output reg o_wr,
 output reg o_rd
 );
 typedef enum logic [$clog2(CHANNELS)-1:0] { CH1 = 2'b00,
 CH2 = 2'b01,
 CH3 = 2'b10,
 CH4 = 2'b11} fsm_states;
 fsm_states ps, ns;
 reg [6:0] ch1_cnt;
 reg [6:0] ch2_cnt;
 reg [6:0] ch3_cnt;
 reg [6:0] ch4_cnt;
always@(posedge i_clk or negedge i_rst_) begin
 if(!_rst_)
 ps <= CH1;
 else
 ps <= ns;
end
always@(*) begin
 case(ps)
 CH1:begin
 if((ch1_cnt == (CH1_WT * UNIT)) && i_rt_lt)
 ns = CH2;
 else if((ch1_cnt == (CH1_WT * UNIT)) && !i_rt_lt)
 ns = CH4;
 else
 ns = CH1;
 end
 CH2:begin
 if((ch2_cnt == (CH2_WT * UNIT)) && i_rt_lt)
 ns = CH3;
 else if((ch2_cnt == (CH2_WT * UNIT)) && !i_rt_lt)
 ns = CH1;
 else
 ns = CH2;
 end
 CH3:begin
 if((ch3_cnt == (CH3_WT * UNIT)) && i_rt_lt)
 ns = CH4;
 else if((ch3_cnt == (CH3_WT * UNIT)) && !i_rt_lt)
 ns = CH2;
 else
 ns = CH3;
 end
 CH4:begin
 if((ch4_cnt == (CH4_WT * UNIT)) && i_rt_lt)
 ns = CH1;
 else if((ch4_cnt == (CH4_WT * UNIT)) && !i_rt_lt)
 ns = CH3;
 else
 ns = CH4;
 end
 endcase
end
always@(*) begin
 case(ps)
 CH1:begin
 o_rd = i_rd[1];
 o_wr = i_wr[1];
 o_data = i_data[1];
 o_addr = i_addr[1];
 end
 CH2:begin
 o_rd = i_rd[2];
 o_wr = i_wr[2];
 o_data = i_data[2];
 o_addr = i_addr[2];
 end
 CH3:begin
 o_rd = i_rd[3];
 o_wr = i_wr[3];
 o_data = i_data[3];
 o_addr = i_addr[3];
 end
 CH4:begin
 o_rd = i_rd[4];
 o_wr = i_wr[4];
 o_data = i_data[4];
 o_addr = i_addr[4];
 end
 endcase
end
always@(posedge clk) begin
 case(ps)
 CH1:begin
 ch1_cnt = ch1_cnt + 1;
 ch2_cnt = 7'd0;
 ch3_cnt = 7'd0;
 ch4_cnt = 7'd0;
 end
 CH2:begin
 ch1_cnt = 7'd0;
 ch2_cnt = ch2_cnt + 1;
 ch3_cnt = 7'd0;
 ch4_cnt = 7'd0;
 end
 CH3:begin
 ch1_cnt = 7'd0;
 ch2_cnt = 7'd0;
 ch3_cnt = ch3_cnt + 1;
 ch4_cnt = 7'd0;
 end
 CH4:begin
 ch1_cnt = 7'd0;
 ch2_cnt = 7'd0;
 ch3_cnt = 7'd0;
 ch4_cnt = ch4_cnt + 1;
 end
 endcase
end
endmodule

module round_robbin_tb;
 parameter UNIT = 6;
 parameter ADDR_WIDTH = 3;
 parameter DATA_WIDTH = 3;
 parameter CHANNELS = 4;
 reg i_rt_lt;
 reg i_clk;
 reg i_rst_;
 reg [ADDR_WIDTH:1] i_addr [CHANNELS:1];
 reg [DATA_WIDTH:1] i_data [CHANNELS:1];
 reg [CHANNELS:1] i_wr; 
 reg [CHANNELS:1] i_rd; 
 wire [ADDR_WIDTH:1] o_addr;
 wire [DATA_WIDTH:1] o_data;
 wire o_wr;
 wire o_rd; 
 round_robbin #(.UNIT(UNIT),
 .ADDR_WIDTH(ADDR_WIDTH),
 .DATA_WIDTH(DATA_WIDTH),
 .CHANNELS(CHANNELS)
 )DUT (i_rt_lt,
 i_clk,
 i_rst_,
 i_addr,
 i_data,
 i_wr,
 i_rd,
 o_addr,
 o_data,
 o_wr,
 o_rd
 );
 always i_clk = #1 ~i_clk;
 initial begin
 $dumpfile("round_robbin.vcd");
 $dumpvars("0,round_robbin_tb");
 i_rt_lt = 0;
 i_clk = 0;
 i_rst_ = 1;
 i_addr[0]=2;
 i_addr[1]=4;
 i_addr[2]=5;
 i_addr[3]=6;
 i_data[0]=4;
 i_data[1]=6;
 i_data[2]=5;
 i_data[3]=1;
 i_wr=$urandom;
 i_rd=$urandom;
 #5;
 i_rst_=0;
 #3;
 i_rst_=1;
 #100;
 $finish;
 end
endmodule

iverilog -g2005-sv -pfileline=1 -E round_robbin.sv round_robbin_tb.sv -Wall

I have no errors in using the above command.

After that, I used vvp a.out, then I get this error message:

a.out 1:syntax error

Can anyone help me?

• jsotola: where are you getting the filename a.out? ... your source files have names starting with round_robbin ... the module also has that same name
• toolic: @jsotola: This is expected. The iverilog command generates a file named a.out when the -o option is not used.

Answer 1

You should not use the -E option on the iverilog command line. That prevents iverilog from creating the compiled version of the Verilog source code required for input to the vvp simulator command.

When using -E, the a.out output file is simply a copy of your 2 input Verilog files run through the preprocessor. It does not compile the Verilog code into the binary file format required by the vvp command. You didn't receive any error with the iverilog command because the preprocessor did not find any errors with the code. However, you do get the error when running the vvp command because the a.out file is the wrong format.

Refer to the Icarus Verilog documentation for details about the -E option.

When I don't use -E, I get plenty of messages from iverilog:

iverilog -g2005-sv -pfileline=1 round_robbin.sv round_robbin_tb.sv -Wall
round_robbin.sv:35: error: Unable to bind wire/reg/memory `_rst_' in `round_robbin_tb.DUT'
round_robbin.sv:35: error: Unable to elaborate condition expression.
round_robbin.sv:83: warning: @* is sensitive to all 4 words in array 'i_data'.
round_robbin.sv:84: warning: @* is sensitive to all 4 words in array 'i_addr'.
round_robbin.sv:89: warning: @* is sensitive to all 4 words in array 'i_data'.
round_robbin.sv:90: warning: @* is sensitive to all 4 words in array 'i_addr'.
round_robbin.sv:95: warning: @* is sensitive to all 4 words in array 'i_data'.
round_robbin.sv:96: warning: @* is sensitive to all 4 words in array 'i_addr'.
round_robbin.sv:101: warning: @* is sensitive to all 4 words in array 'i_data'.
round_robbin.sv:102: warning: @* is sensitive to all 4 words in array 'i_addr'.
round_robbin.sv:107: error: Unable to bind wire/reg/memory `clk' in `round_robbin_tb.DUT'
posedge clk
round_robbin_tb.sv:40: warning: ignoring out of bounds l-value array access i_addr[0].
round_robbin_tb.sv:44: warning: ignoring out of bounds l-value array access i_data[0].
4 error(s) during elaboration.

To fix the error messages, in the round_robbin module, change _rst_ to i_rst_, and change clk to i_clk.

I get another error when I run the simulation. You must remove the quotes from the $dumpvars line:

 $dumpvars(0,round_robbin_tb);