How does Verilog code run when it finds positive edge of clock?

Question

rd=1;
case1=2; 
i=2; 
n1=23; 
always @(posedge clka) 
begin 
 counter=counter+1; 
 if (rd==1) begin 
 #5 window[i]<=douta; //~~~~~~~~~~~ Statement1 
 case(i) 
 case1: addra=n1;
 case2: addra=n2;
 endcase 
 #5 addra<=addra+1; //~~~~~~~~~~~Statement2 
 #5 i<=i+1; 
 end 
end 

The statements inside an always block in Verilog are sequential. At the positive edge of clock :

counter=counter+1 
if (rd==1) (true)

My confusion is that as case statement occurs first because window[i]=douta (after 5 unit time). After this statement 2 occur or statement 1 and statement occur at same time.

How do statements inside the always block in this case run?

Answer 1

In this case, the execution order should be as follows (in this exact order):

Time X: if-statement
Time X+5: case
Time X+5: Statement 1
Time X+10: Statement 2

What you are running into is confusion about blocking vs non-blocking assignment. This is a nice example as to why it is called non-blocking assignment. When you hit the line #5 window[i]<=douta;, the simulator will wait 5 time units, then schedule window[i] to take on the value of douta at the end of the current time step. Because you used the non-blocking assignment operator, the execution of the always block continues to the next statements, which is the case statement. Since the assigns here are blocking assignments, they are executed immediately. Then, the #5 is hit (after the case), so the scheduler schedules the next execution for 5 time units in the future. Then it moves on to anything else it needs to do. Finally, it comes back (still within time step X+5) and completes all the non-blocking assignments (like window[i]<=douta). Thats why you are seeing what looks like non-inorder execution of your always block.