Why does this file give me syntax error: I give up in verilog program?

Question

Why does this Verilog code give me the following syntax error?

I give up in verilog program

This is my code:

module circuit_lee (a, b, c, d, e);
 input a, b, c, d, e;
 output y;
 wire w1, w2, w3, w4;
 or o1(w1, a, b);
 or o2(w4, w3, w2);
 and a1(w2, c, d);
 and a2(y, w4, e);
 not n1(w3, w1);
endmodule

`include "circuit_lee.v"
module circuit_lee_tb;
 reg a, b, c, d, e;
 wire y;
 circuit_lee add1(a, b, c, d, e, y);
 initial 
 begin
 $dumpfile("circuit_lee.vcd");
 $dumpvars(0,circuit_lee_tb);
 a = 0; b = 0; c = 0; d = 0; e = 0;
 #1
 a = 0; b = 0; c = 0; d = 1; e = 0;
 #1
 a = 0; b = 0; c = 1; d = 0; e = 0;
 #1
 a = 0; b = 0; c = 1; d = 1; e = 0;
 #1
 a = 0; b = 1; c = 0; d = 0; e = 0;
 #1
 a = 0; b = 1; c = 0; d = 1; e = 0;
 #1
 a = 0; b = 1; c = 1; d = 0; e = 0;
 #1
 a = 0; b = 1; c = 1; d = 1; e = 0;
 #1
 a = 1; b = 0; c = 0; d = 0; e = 0;
 #1
 a = 1; b = 0; c = 0; d = 1; e = 0;
 #1
 a = 1; b = 0; c = 1; d = 1; e = 0;
 #1
 a = 1; b = 1; c = 0; d = 0; e = 1;
 #1
 a = 1; b = 1; c = 0; d = 1; e = 1;
 #1
 a = 1; b = 1; c = 1; d = 0; e = 1;
 #1
 a = 1; b = 1; c = 1; d = 1; e = 1;
 #1
 end
endmodule

• Marcus Müller: Verilog is just the language. That error is generated by a tool that deals with verilog. You need to tell us which tool!

Answer 1

When your simulator does not give you a very helpful error message, you can try your code on other simulators on EDA playground. For example, using the Cadence simulator, you get this message:

 output y;
 |
xmvlog: *E,NOPORT (testbench.sv,3|11): input/output/inout 'y' not declared in port list [12.3.2(IEEE)].

To fix that error, change:

module circuit_lee (a, b, c, d, e);

to:

module circuit_lee (a, b, c, d, e, y);

There is another syntax error after that. All statements in Verilog must end with a semicolon. Add it after the last #1:

 #1;
 end

Here is the complete code on EDA playground, which compiles without errors.

Answer 2

You declared output y; but it does not appear in your port list.

You are using very old Verilog-1995 port syntax which requires that you mention each port twice, sometimes 3 times. I strongly suggest using the Verilog-2001/SystemVerilog ANSI-style port list which would look like this:

module circuit_lee (
 input a, b, c, d, e,
 output y 
);