Passing register value in Verilog module as input to another module

Question

I use the XADC IP, for which a module na7_chseq_xadc is used to write the digital data from the ADC in registers adc2_out, adc3_out, and adc10_out. In this module, the XADC IP is instantiated.

module na7_chseq_xadc(
input clk,
input vauxp2,
input vauxn2,
input vauxp3,
.......
);
register [11:0] adc2_out, adc3_out, adc10_out;
....
adc2_out=data;
.....
adc3_out=data;
....
adc10_out=data;
....
);
endmodule

I have another module within the same project (separate Verilog file) which generates the control signals and serial data for a DAC connected to the same board (Nexys A7). The module name is pmod_dac_test.

module pmod_dac_test(
input [11:0] auxp2,
input [11:0] auxp3,
input [11:0] auxp10,
input clk,
output sclk_out,
output sd_out,
output sync_out
);
.....
);
endmodule

The values in the registers adc2_out, adc3_out, and adc10_out from "na7_chseq_xadc" need to be passed as inputs to module "pmod_dac_test" (auxp2, auxp3, auxp10). I understand the module "pmod_dac_test" can be instantiated within "na7_chseq_xadc". Is it a correct way to pass the values?
If yes, will the following work? Is it okay to instantiate only 3 input ports of the module?

//within na7_chseq_xadc
pmod_dac_test inst1(
 .auxp2(adc2_out);
 .auxp3(adc3_out);
 .auxp10(adc10_out)
);

Answer 1

Yes, that is the correct way to connect signals to a module instance, but you need to use commas, not semicolons, between connections.

Also, you must make connections to all ports.

Here is a code example that compiles without errors:

module pmod_dac_test(
 input [11:0] auxp2,
 input [11:0] auxp3,
 input [11:0] auxp10,
 input clk,
 output sclk_out,
 output sd_out,
 output sync_out
);
endmodule
module na7_chseq_xadc(
 input clk,
 input vauxp2,
 input vauxn2,
 input vauxp3
);
reg [11:0] adc2_out, adc3_out, adc10_out, data;
always @* begin
 adc2_out=data;
 adc3_out=data;
 adc10_out=data;
end
//within na7_chseq_xadc
pmod_dac_test inst1 (
 .clk(clk),
 .auxp2(adc2_out),
 .auxp3(adc3_out),
 .auxp10(adc10_out),
 .sclk_out(),
 .sd_out(),
 .sync_out()
);
endmodule

You need to decide what to connect to the following pmod_dac_test output ports:

.sclk_out(),
.sd_out(),
.sync_out()

• Suhanya: Right. I see what happens now. The output ports are connected to top level pins. When I instantiated the "pmod_dac_test" module again, it raised off a lot of constraint errors - the "pmod_dac_test" modules and a "copy" of the same (the instance) have output ports connected to the same top level pins. I think instantiating the module was a bad idea - it had the communication protocol code in it. I shall try to add the ADC code into the "pmod_dac_test" itself - no instances (copies), and just one file to handle. Shall try this for now. Thanks.
• toolic: @Suhanya: You're welcome. Since you are a new user: What should I do when someone answers my question?