How can I use clk as an input port in Verilog?

Question

I am working on a simple FSM that counts to 3 and will either output 1 or 0 based on if the number of times a 1 is counted on is mod3 = 0.

FSM.sv

module FSM (input logic in, clk,
 output logic out);
 reg [1:0] state;
 reg [1:0] w;
 
 initial
 state = 2'b00;
 //state change logic
 always @(posedge clk) begin
 case({state,in})
 {2'b0,1'b0}:
 w = 2'b00;
 {2'b0,1'b1}:
 w = 2'b01;
 {2'b1,1'b0}:
 w = 2'b01;
 {2'b1,1'b1}:
 w = 2'b10;
 {2'b10,1'b0}:
 w = 2'b10;
 {2'b10,1'b1}:
 w = 2'b00;
 endcase
 end
 
 always @(w)
 state = w;
 //update output based on state
 always @(negedge clk) begin
 
 case(state)
 2'b00: out = 1'b1;
 2'b01: out = 1'b0;
 2'b10: out = 1'b0;
 endcase
 end
 
endmodule

FSM_tb.sv

`timescale 1ns / 1ps
module tb ();
 logic in;
 logic out;
 logic clk; 
 
 // instantiate device under test
 FSM dut (in, out, clk);
 // 2 ns clock
 initial 
 begin 
 clk = 1'b1;
 forever #10 clk = ~clk;
 end
 initial
 begin
 
 #0 in = 1'b0;
 
 #20 in = 1'b1;
 
 #20 in = 1'b0;
 
 #20 in = 1'b1;
 
 #20 in = 1'b0;
 
 #20 in = 1'b1;
 
 end
 
endmodule

You can see that in my FSM.sv file I am checking the input and current state at the posedge of the clock which is an input to the module. When it is the negedge of the clock it will update the output based on the state.

My issue is that in my FSM_tb.sv you can see I am trying to set the clk to a cycle of 20ns and it gives the error in Modelsim console of:

Variable '/tb/clk', driven via a port connection, is multiply driven.

If I remove the clk from my FSM.sv file it will remove the error, but obviously my posedge/negedge blocks will no longer function. How am I supposed to correctly use the clk within a module?

• Mikef: A clock signal is used as a port rather than a parameter.

Answer 1

Your port connections are out of position.

Try

FSM dut (in, clk, out); // positional

or

FSM dut (.in, .out, .clk); // by .name

or

FSM dut (.*); // match all by name

Also, your test runs forever. Put a #20 $finish at the end of your last initial block.