How to use IF/ELSE conditions in xemacs verilog-mode /*AUTO_TEMPLATE();*/

Question

When using autoverilog to instantiate modules the character @ defines the module number. How do I instantiate many instances of the same module and tie some of the IO ports based on the IF/ELSE condition of module number?

The non-working pseudocode implementation ("" represent the autotemplating conditions) is here:

/*module AUTO_TEMPLATE (
.s (s@[]),
"if @==0"
.d (x),
"else if @==1"
.d (y),
"else"
.d (z),
"endif"
);*/
module one (/*AUTOINST*/)
module two (/*AUTOINST*/)
module three (/*AUTOINST*/)

The desired outcome should be:

module one(
.s (s0),
.d (x)
);
module two(
.s (s1),
.d (y)
);
module three(
.s (s2),
.d (z)
);

The closest example I found is here, but the implementation of IF/ELSE is inline, does not seem to be practical for many conditional statements and would be difficult to read. Is there a way to achieve my goal that would look something like the pseudo implementation I provided?

Answer 1

in my view it is not possible to used if/else Directly in port list during instantiation, however you can achive your result by using generate constructs and concatenation to create the instances. with the desired condition. here is updated code:

module AUTO_TEMPLATE #(parameter AUTOINST_NUM=3) ( input [AUTOINST_NUM-1:0] s, output reg [AUTOINST_NUM-1:0] d );

genvar i; generate for (i = 0; i < AUTOINST_NUM; i = i + 1) begin : gen_block if (i == 0) begin one #(i) u ( .s(s[i]), .d(d[i]) ); end else if (i == 1) begin two #(i) u ( .s(s[i]), .d(d[i]) ); end else begin three #(i) u ( .s(s[i]), .d(d[i]) ); end end endgenerate

endmodule

module one #(int instance_number) ( input s, output reg d );

endmodule

module two #(int instance_number) ( input s, output reg d );

endmodule

module three #(int instance_number) ( input s, output reg d );

endmodule

• toolic: use code tags...