Verilog if-else-if syntax

Question

I want to understand the if else if priority and working for Verilog. In my code I can't seem to get to the 3rd condition and statement of the if else if construct. Why?

module alu #(parameter WIDTH=8) (in_a, in_b, opcode, alu_out, a_is_zero);
 input [2:0] opcode;
 input [WIDTH-1:0] in_a, in_b;
 output reg [WIDTH-1:0] alu_out;
 output reg a_is_zero;
 always @*
 begin
 a_is_zero=|in_a?0:1;
 if(opcode==000)begin
 alu_out=in_a; 
 end else if (opcode==001) begin
 alu_out=in_a; end
 else if(opcode==010) begin
 alu_out= in_b+in_a; end
 else begin alu_out=in_a; end 
 end 
endmodule

failing to read the third condition-statement

• dave_59: Does this answer your question? Please explain the following integer constant used in verilog

Answer 1

You need to add a b base specifier to your 3-bit constants. In your code, 010 is the decimal value ten, not two. You declared opcode as a 3-bit signal, which means it can have decimal values in the range 0-7. Therefore, decimal 10 is not in the range, and if(opcode==010) will never be true. If a number is specified without a base, Verilog defaults to decimal format.

I added the 3'b prefix to your 3 constants below:

if(opcode==3'b000)begin
 alu_out=in_a; 
 end else if (opcode==3'b001) begin
 alu_out=in_a; end
 else if(opcode==3'b010) begin