Synthesis Verilog Delay (#x), syntax question

Question

I used an IP from Lattice FPGA and looked in their code.

they use this bullets of verilog code there:

 // -----------------------------------------------------------
// gclk gate control2 on falling edge to prevent runt 
// -----------------------------------------------------------
always @(negedge hclk or negedge reset_n) begin
 if (~reset_n) begin
 gate_clk_ctl2 <= #1 1'b1;
 end
 else begin
 gate_clk_ctl2 <= #1 !orc_ack_1d;
 end
end

....

..

.

 //-------------------------------------------------------------------
// Latch data and address into internal reg clocked by hclk
//-------------------------------------------------------------------
always @(posedge hclk or negedge reset_n) begin
 if (~reset_n) begin
 reg_di[25:0] <= #1 26'h0000000;
 end
 else begin
if (pc_rdy_pulse) begin
 reg_di[25:0] <= #1 sreg_di[25:0];
 end
 end
end

I don't understand this syntax what this "#1" doing? what this logic does?

I know #x in verilog is delay.. but this is synthesizable code, so I dont understand how does it work.

Thanks.

• copper.hat: Probably so they can see the propagation during simulation?

Answer 1

Delays specified in this way only affect simulation; they are removed during synthesis.