Verilog - Use integer constant to define signal width

Question

I have a module which takes two parameters, ParameterOne and ParameterTwo. I use their ratio a lot, so I gave it a name const integer Ratio = ParameterOne/ParameterTwo.

I want to have a signal whose width is this ratio, so I defined a signal logic [Ratio-1:0] wires. However, I get the error message Range must be bounded by constant expressions. This leaves me perplexed, as this range is bounded by a constant expression (I explicitly declare it to be const).

Does anyone here know why it's complaining about this code?

Answer 1

Although the terminology sounds similar, there are big differences between a constant expression and a const variable.

A constant expression is an expression whose operands are made up entirely of parameters and literals. Its value gets resolved as part of the compilation and elaboration process, before time 0.

A const variable is a variable that is written once at initialization, and you can never write to it again. The initialization can happen at any time based on the beginning of the variables lifetime, and can include the values of other variables that are not const. The earliest is at time 0 for static variables.

You should write this using a parameter or localparam`

localparam int Ratio = ParameterOne/ParameterTwo;

A localparam is just a parameter that cannot be overridden.

• Jarred Allen: Thanks for this answer. I changed it to use localparam and it now works. I guess I just assumed that const would be a compile-time constant (like it is in C and related programming languages), so the fact that verilog does it differently threw me off.
• dave_59: The behavior of const in C and SystemVerilog is exactly the same--they are write-once variables. It's just there are different places where constant expressions are required, the the bit-width of a variable declaration is one of them. In C, you cannot use a const variable to declare the size of a static array, but you can for a non-static array.